3D Inductor Fabrication for Flip Chip Modules
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Solution Overview
Problem
Conventional planar inductors suffer from parasitic capacitance issues and are limited in reducing chip size due to their two-dimensional design, which restricts the formation of a toroid structure and hinders efficient electromagnetic coupling in flip chip modules.
Innovation Solution
A method for fabricating a carrier with a three-dimensional inductor involves a multi-layered structure using photoresist and metal layers on a substrate, creating inductive portions with varying heights and connections to reduce layout area and alter magnetic flux direction from normal to horizontal.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If a planar inductor design is used, then the inductor can be formed in a single plane, but parasitic capacitance disturbance occurs and chip size cannot be decreased
Solution Approach 1:
The patent transitions from a planar two-dimensional inductor design to a three-dimensional structure by adding vertical layers. Multiple metal layers are stacked with dielectric layers in between, creating a multi-layered inductor configuration that utilizes the third dimension (height) to achieve toroid structure while reducing parasitic capacitance effects through increased separation between conductive elements.
2Ease of manufacture
If a planar inductor design is used, then the manufacturing process is simpler, but the chip size cannot be decreased
Solution Approach 1:
The patent employs multi-layer stacking to build the inductor vertically, allowing the magnetic core and windings to be arranged in three dimensions rather than confined to a single plane. This vertical arrangement reduces the horizontal footprint and enables smaller chip size while maintaining inductor functionality.
Solution Approach 2:
The patent implements a nested structure where multiple windings are arranged concentrically around a magnetic core in a toroid configuration. The windings are positioned at different heights and radial distances, creating a compact nested arrangement that maximizes space utilization and reduces overall chip area.
3Ease of manufacture
If a planar inductor design is used, then the structure is simpler to form, but it only creates a vortex structure instead of a toroid structure
Solution Approach 1:
The patent utilizes vertical stacking of metal and dielectric layers to create the toroid shape, where the magnetic core forms a closed loop and windings are wrapped around it in multiple layers. This three-dimensional construction enables true toroid geometry with magnetic flux contained within the core, unlike planar vortex structures.
Data Source
AI summary
A method for fabricating a carrier with a three-dimensional inductor comprises the steps of providing a substrate having a protective layer; forming a first photoresist layer on the protective layer; patterning the first photoresist layer to form a second opening and a plurality of disposing slots; forming a first metal layer in second opening and disposing slots; removing the first photoresist layer; forming a first dielectric layer on the protective layer; forming a second photoresist layer on the first dielectric layer; patterning the second photoresist layer to form a plurality of slots; forming a second metal layer in slots to form a plurality of inductive portions; removing the second photoresist layer; forming a second dielectric layer on the first dielectric layer; forming a third photoresist layer on the second dielectric layer; patterning the third photoresist layer to form a plurality of slots; and forming a third metal layer in slots.