3D Inductor Package Layout Without Thicker Passivation
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Solution Overview
Problem
The challenge in forming a 3D inductor structure on a semiconductor substrate is the difficulty in increasing its height without significantly increasing costs due to the need for a thicker passivation layer, which is costly.
Innovation Solution
A semiconductor device package design incorporating a substrate, patterned conductive layers, dielectric layers, and encapsulation layers, with specific configurations and manufacturing methods to form a 3D inductor structure that maintains a reduced package size while enhancing electrical conductivity and inductance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the height of the 3D inductor structure is increased to improve inductance and electrical conductivity, then the inductance and conductivity are improved, but the package size increases and cost increases due to thicker passivation layer requirements
Solution Approach 1:
The patent embeds the inductor structure within the substrate itself by forming conductive layers and dielectric layers in a nested configuration. The inductor is integrated into the substrate thickness rather than extending above it, allowing the inductor to be nested within the existing package structure without increasing overall package height.
Solution Approach 2:
The patent transitions from a traditional planar inductor design to a three-dimensional structure formed within the substrate depth. By utilizing the vertical dimension within the substrate rather than extending above the substrate surface, the design achieves higher inductance through increased conductor path length without increasing the package's external dimensions.
2Reliability
If the height of the 3D inductor structure is increased to improve inductance and electrical conductivity, then the inductance and conductivity are improved, but the manufacturing cost increases due to thicker passivation layer requirements
Solution Approach 1:
The inductor structure is nested within the substrate using standard semiconductor fabrication layers. This approach eliminates the need for additional thick passivation layers that would be required to protect elevated inductor structures, thereby reducing manufacturing costs while maintaining the desired inductance values.
Solution Approach 2:
The substrate itself serves as the housing and protective structure for the inductor, eliminating the need for separate thick passivation layers. The existing substrate and its standard protective layers provide sufficient protection, reducing material costs and simplifying the manufacturing process.
3Length of stationary object
If the thickness of the passivation layer is increased to accommodate a taller 3D inductor structure, then the inductor structure can be accommodated, but the manufacturing cost increases
Solution Approach 1:
The inductor structure is nested within the substrate depth, eliminating the need for increased passivation layer thickness. The inductor fits within the existing substrate and standard passivation layer thicknesses, avoiding additional material costs and processing steps.
Solution Approach 2:
Instead of increasing passivation layer thickness to accommodate a taller inductor, the patent inverts the approach by reducing the inductor's vertical extent and integrating it within the substrate. This reversal eliminates the need for thicker passivation layers while still achieving the desired inductance through three-dimensional conductor routing.
Data Source
AI summary
A semiconductor device package includes a substrate, a first patterned conductive layer, a second patterned conductive layer, a dielectric layer, a third patterned conductive layer and a connector. The substrate has a top surface. The first patterned conductive layer is on the top surface of the substrate. The second patterned conductive layer contacts the first patterned conductive layer. The second patterned conductive layer includes a first portion, a second portion and a third portion. The second portion is connected between the first portion and the third portion. The dielectric layer is on the top surface of the substrate. The dielectric layer covers the first patterned conductive layer and surrounds the second portion and the third portion of the second patterned conductive layer. The first portion of the second patterned conductive layer is disposed on the dielectric layer. The third patterned conductive layer is on the second patterned conductive layer, and the connector is directly on the third patterned conductive layer.