3D Inductor and Transformer Vertical Integration
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Solution Overview
Problem
Two-dimensional integration of inductors and transformers in semiconductor ICs leads to increased chip area requirements, higher metal line resistance, and unwanted noise due to magnetic flux coupling with other components, limiting density and quality factor (Q) of these components.
Innovation Solution
A three-dimensional semiconductor structure using an interposer with conductive bumps and through-substrate vias (TSVs) to form inductors and transformers, which reduces magnetic flux penetration and allows for larger, thicker conductive materials, thereby increasing the Q factor and reducing parasitic coupling.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If inductors and transformers are integrated in 2-D on the chip, then integration density is improved, but chip area is increased and metal line resistance increases
Solution Approach 1:
The patent transitions from 2-D planar integration to 3-D vertical integration by stacking multiple conductive layers above and below the chip surface. Conductive patterns are formed in metallization layers on both the front and back sides of the chip, utilizing the third dimension (vertical space) to increase integration density without proportionally increasing chip area.
2Productivity
If feature sizes are reduced to increase integration density, then more components fit on chip, but metal line resistance increases
Solution Approach 1:
The patent employs composite conductive structures combining multiple materials including copper or aluminum metallization layers, conductive bumps (solder, eutectic, or copper pillars), and through-substrate vias. This composite approach allows optimization of each material's properties to minimize resistance while maintaining small feature sizes for high integration density.
Solution Approach 2:
The patent changes physical parameters by using thicker conductive patterns in vertical stacks rather than thin 2-D traces. The conductive bumps provide low-resistance vertical interconnects, and the multi-layer structure increases effective conduction path area, thereby reducing resistance despite reduced lateral feature sizes.
3Productivity
If inductors and transformers are placed on the chip, then integration is improved, but magnetic flux couples with other devices creating noise
Solution Approach 1:
The patent directs magnetic flux primarily in the vertical dimension through 3-D conductor geometries and stacked configurations. By orienting conductive patterns vertically and using through-substrate vias, the magnetic field is confined more effectively, reducing lateral flux coupling with adjacent devices and minimizing noise interference.
Solution Approach 2:
The patent introduces magnetic shielding layers or ground planes between the inductor/transformer structures and other sensitive devices. These intermediary elements act as barriers to magnetic flux, preventing coupling with transistors, metal lines, and interconnects, thereby reducing noise while maintaining integration.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The 3D structure effectively reduces parasitic coupling and increases the quality factor of inductors and transformers by directing magnetic flux parallel to the chip surface and using larger, thicker conductive materials, while also potentially lowering production costs.
Implementation Method 1
inductors and transformers are commonly used... form coils that generate magnetic flux
Implementation Method 2
The magnetic flux may couple with devices in the chip, such as transistors, metal lines, and/or interconnects to create unwanted noise
Data Source
AI summary
In accordance with an embodiment, a semiconductor device comprises a semiconductor die, an interposer, and conductive bumps bonding the semiconductor die to the interposer. The semiconductor die comprises a first metallization layer, and the first metallization layer comprises a first conductive pattern. The interposer comprises a second metallization layer, and the second metallization layer comprises a second conductive pattern. Some of the conductive bumps electrically couple the first conductive pattern to the second conductive pattern to form a coil. Other embodiments contemplate other configurations of coils, inductors, and/or transformers, and contemplate methods of manufacture.