3D Inductor and TSV Layout for Smaller Stacked IC Packages
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing integrated circuits face challenges in efficiently implementing passive devices like inductors due to their larger area requirements, which can lead to increased costs and reduced yield.
Innovation Solution
The integration circuit design includes a structure for interconnecting stacked dies, where an inductor is efficiently disposed based on this structure, with the inductor overlapping vertical interconnects in the vertical direction, thereby reducing spatial constraints and area requirements.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If passive devices like inductors are implemented in traditional planar configurations, then they can perform their electrical function, but they occupy large area which increases cost and reduces yield
Solution Approach 1:
The patent transitions from planar 2D inductor layouts to a 3D vertical configuration where the inductor is positioned above the substrate and overlaps with through-silicon vias in the vertical direction. This dimensional change allows the inductor to occupy less footprint area while maintaining its electrical performance through proper vertical stacking and overlapping design.
2Area of stationary object
If the circuit area is reduced through miniaturization, then manufacturing cost decreases and yield improves, but implementing passive devices becomes more difficult
Solution Approach 1:
The patent divides the inductor structure into multiple segments: the inductor element positioned in the upper layer, through-silicon vias penetrating the substrate, and conductive interconnects in the lower layer. This segmentation allows each component to be optimized independently while facilitating modular manufacturing processes and assembly.
Solution Approach 2:
The patent implements a nested configuration where the inductor is positioned above the substrate and overlaps with the through-silicon vias in the vertical direction. The conductive interconnects are nested within the vertical interconnect structure, creating a compact multi-layer arrangement that reduces overall area while maintaining manufacturability through standardized vertical stacking processes.
3Area of stationary object
If vertical interconnects are used to overlap with the inductor, then area is reduced, but the complexity of the interconnection structure increases
Solution Approach 1:
The through-silicon vias serve multiple functions: they provide vertical electrical interconnection between layers and simultaneously act as part of the inductor structure through which the inductor windings are formed. The conductive interconnects similarly serve both as connection elements and as structural components of the vertical interconnect system, reducing overall device complexity despite the three-dimensional arrangement.
Data Source
AI summary
Provided is an integrated circuit including a first die including a first substrate and a plurality of through silicon vias (TSVs) penetrating through the first substrate, and a second die disposed below the first die in a vertical direction perpendicular to an in-plane direction of the first die and including a second substrate and a plurality of conductive interconnects electrically connected to separate, respective TSVs of the plurality of TSVs, wherein the first die further includes an inductor in at least one first layer over the first substrate in the vertical direction, and the inductor at least partially overlaps at least one TSV of the plurality of TSVs in the vertical direction.