3D Inductors in Silicon Substrates for High-Q Factor ICs
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Solution Overview
Problem
Integrated circuits (ICs) face limitations in inductance and efficiency due to high resistance in metal layers, making them unsuitable for applications beyond ultra-high frequency ranges and contributing to significant switching losses, while co-packaged discrete inductors are bulky and costly.
Innovation Solution
Forming inductors within the unused bulk silicon substrate of ICs through 3D post-processing, using trenches to create high-density, high-quality factor inductors that integrate vertically with active circuitry, allowing for efficient energy transfer and reduced packaging complexity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If inductive components are fabricated using metal layers in IC, then integration is achieved, but inductance is limited to relatively low values and quality factor is limited by high resistance
Solution Approach 1:
The patent transitions from planar metal layer inductors to three-dimensional vertical inductor structures formed in the bulk silicon substrate. This dimensional change enables significantly higher inductance values and quality factors by utilizing the vertical dimension for magnetic flux containment and reduced parasitic resistance, while maintaining integration with the IC circuitry.
2Device complexity
If inductive components are fabricated using metal layers in IC, then integration is achieved, but switching losses are significant
Solution Approach 1:
The vertical three-dimensional inductor structure reduces parasitic resistance and optimizes current distribution, thereby reducing switching losses compared to planar metal layer inductors while maintaining integration with the IC.
3Reliability
If co-packaged discrete inductors are used, then inductance requirements are met, but package size is large and complexity increases
Solution Approach 1:
The patent merges the inductor and IC into a single integrated structure by forming the inductor directly in the bulk silicon substrate of the IC. This consolidation eliminates the need for separate discrete inductors and complex co-packaging, reducing overall package size and complexity while maintaining required inductance performance.
4Reliability
If co-packaged discrete inductors are used, then inductance requirements are met, but package cost increases
Solution Approach 1:
The integration of the inductor directly into the IC substrate eliminates the need for separate discrete inductor components and complex packaging processes, thereby reducing manufacturing costs while maintaining required inductance performance.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables high-quality, low-loss inductors that support larger peak currents and improve alternating current resistance, reducing overall solution size and cost while maintaining efficiency across various frequency ranges.
Implementation Method 1
forming a coil in one or more metal layers of the IC
Data Source
AI summary
In an integrated circuit (IC), a semiconductor substrate has a first side and an opposite second side. The second side has a trench. Circuitry is on the first side. An inductive structure is within the trench. The inductive structure is connected to the circuitry through vias in the semiconductor substrate. The semiconductor substrate is mounted on a package substrate. At least a portion of the inductive structure contacts the package substrate. The circuitry is coupled to the inductive structure through wires to the package substrate.