3D Integrated Circuit Architecture With Segmented Substrate Layers
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Solution Overview
Problem
Modern semiconductor circuits face competing processing requirements due to the need for optimized performance characteristics of various components, such as enhanced speed for logic circuits and charge storage capacity for memory circuits, within a reduced substrate surface area.
Innovation Solution
The design structure includes separate substrate layers for different memory arrays and logic circuit elements, each optimized for specific performance and power specifications, allowing for individual optimization of devices and circuits, with logic devices coupled to memory arrays and unique power supplies.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If separate substrate layers are used for different memory arrays and logic circuit elements, then individual optimization of performance and power specifications is improved, but device complexity increases
Solution Approach 1:
The integrated circuit is divided into multiple separate substrate layers, each dedicated to specific circuit types (logic circuits on first substrate, memory circuits on second substrate). This segmentation allows independent optimization of each layer's devices and interconnect structures for their specific performance requirements, resolving the contradiction between adaptability and complexity by organizing the complex system into manageable, independently optimizable segments.
Solution Approach 2:
The patent transitions from a planar two-dimensional layout to a three-dimensional stacked architecture with multiple substrate layers vertically arranged. This dimensional change allows different circuit types to be separated in the vertical dimension while maintaining compact overall footprint, enabling individual optimization of each layer without proportionally increasing the horizontal substrate area.
2Speed
If different crystallographic orientations are used for separate field effect transistors, then charge carrier mobility is optimized, but manufacturing complexity increases
Solution Approach 1:
Field effect transistors are segmented into different groups based on their performance requirements, with each group fabricated on substrates with specific crystallographic orientations optimized for their function. Logic circuit transistors use orientations optimized for high-speed operation, while memory circuit transistors use orientations optimized for their specific characteristics, allowing mobility optimization without requiring all devices to undergo complex multi-orientation fabrication.
Solution Approach 2:
Different regions of the integrated circuit structure are assigned different crystallographic orientations based on local performance requirements. The first substrate layer contains transistors with orientations optimized for logic circuit speed, while the second substrate layer contains transistors with orientations optimized for memory circuit characteristics, allowing each local region to have the quality needed for its specific function.
Data Source
AI summary
An integrated circuit design, structure and method for fabrication thereof includes at least one logic device layer and at least two additional separate memory array layers. Each of the logic device layer and the at least two memory array layers is independently optimized for a particular type of logic device or memory device disposed therein. Preferably also disposed within the logic device layer are array sense amplifiers, memory array output drivers and like higher performance circuitry otherwise generally disposed within memory array layer substrates. All layers may be independently powered to provide additional performance enhancement.