3D Integrated Thermoelectric Generator with Copper-Filled TSVs
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Solution Overview
Problem
Existing thermoelectric generators (TEGs) with out-of-plane heat flux configurations face inefficiencies in power yield per unit footprint area and conversion efficiency due to thermal losses and poor thermal coupling, despite their potential for miniaturization and integration in microelectronic devices.
Innovation Solution
The Z-device structure features a substrate with hill-top and valley-bottom junction metal contacts, alternately p-doped and n-doped thin film segments on inclined flanks of low thermal conductivity material, and through-silicon vias (TSVs) filled with copper to create low thermal resistance heat conduction paths, reducing internal heat transfer by voiding dielectric fillers and using offset copper pillars to enhance thermal resistance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If out-of-plane heat flux configuration is used, then thermal coupling is improved, but thermal losses increase reducing power yield per unit area
Solution Approach 1:
The device is divided into multiple unit cells with alternating p-type and n-type thermoelectric legs, where each unit cell operates independently to convert heat flux into electrical energy. This segmentation allows for optimized thermal paths in each cell while maintaining overall device performance
Solution Approach 2:
Different regions of the device are assigned different thermal conductivities: the substrate and heat sink have high thermal conductivity for efficient heat distribution and removal, while the thermoelectric legs have optimized thermal conductivity to balance heat conduction with electrical power generation. This local optimization resolves the contradiction between thermal coupling and thermal losses
2Area of stationary object
If miniaturization is pursued, then integration in microelectronic devices is enabled, but thermal management becomes more challenging
Solution Approach 1:
The device transitions from planar in-plane heat flow to out-of-plane heat flux configuration, utilizing the vertical dimension for heat transport. This dimensional change enables better thermal management in miniaturized devices by creating dedicated thermal paths perpendicular to the substrate, improving heat removal efficiency without increasing footprint area
Solution Approach 2:
A substrate with high thermal conductivity is introduced as an intermediary between the heat source and heat sink, enabling efficient thermal management in miniaturized devices. The substrate acts as a thermal mediator that distributes heat uniformly across the device while maintaining compact dimensions
3Ease of manufacture
If conventional planar processing is used, then manufacturing is simplified, but power yield per unit area is reduced
Solution Approach 1:
The device structure is designed to be compatible with conventional planar processing techniques used in microelectronics and MEMS fabrication, allowing the same manufacturing infrastructure to produce both standard electronic devices and thermoelectric generators. This universality maintains ease of manufacture while achieving improved power yield through the out-of-plane heat flux configuration
Solution Approach 2:
The thermoelectric legs are directly deposited and patterned on the substrate using standard thin-film deposition and photolithography techniques, eliminating the need for separate complex assembly processes. The device structure itself facilitates the manufacturing process by aligning with conventional planar processing workflows
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration significantly increases power yield per unit area and conversion efficiency by minimizing thermal losses and improving thermal coupling, making the TEGs more suitable for energy harvesting applications.
Implementation Method 1
through-silicon vias (TSVs) filled with copper to create low thermal resistance heat conduction paths
Implementation Method 2
low thermal conductivity material
Implementation Method 3
thermoelectric generators (TEGs) are earnestly investigated as low enthalpy waste heat exploitation devices
Data Source
AI summary
Dices of integrated Z-device structures on a substrate wafer of a 3D integrated thermo-electric generator (iTEG) may be stacked in a tri-dimensional heterogeneous integration mode, without or with interposer wafer dices, in coherent thermal coupling among them. Through silicon vias (TSVs) holes through the thickness of the semiconductor crystal of substrate of the dices of integrated Z-device structures in geometrical projection correspondence with valley bottom metal junction contacts, and through silicon vias (TSVs) holes through the thickness of the semiconductor crystal of interposer dices, in geometrical projection correspondence with the hill-top metal junction contacts of the coupled Z-device structures, have a copper or other good heat conductor filler, form low thermal resistance heat conduction paths through the stacked Z-device structures. Thermoelectrically generated current is gathered from every integrated Z-device of a multi-tier iTEG operating in an out-of-plane heat flux configuration.