3D Integrated Wiring Structure for High-Density Memory
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Solution Overview
Problem
Planar memory cell technologies face challenges in scaling and cost as feature sizes approach limits, necessitating a transition to 3D integrated wiring structures to enhance memory density.
Innovation Solution
A method for forming a 3D integrated wiring structure involves creating a dielectric layer in a substrate, forming conductive contacts on both sides, and connecting them through a bonding process, enabling efficient interconnects and wiring through thick semiconductor layers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If planar memory cell scaling is continued to increase memory density, then memory density improves, but manufacturing complexity and cost increase significantly
Solution Approach 1:
The patent transitions from planar (2D) memory cell architecture to three-dimensional (3D) stacked architecture. Multiple memory layers are stacked vertically with interlayer wiring structures connecting different layers, thereby increasing memory density without proportionally increasing manufacturing complexity by utilizing the vertical dimension.
Solution Approach 2:
The memory structure is divided into multiple discrete layers stacked vertically, with each layer containing memory cells and wiring structures. This segmentation allows for modular manufacturing processes and enables the use of through-silicon vias (TSVs) and interlayer connections to integrate the stacked layers, thereby increasing density while managing complexity through standardized interconnection techniques.
2Quantity of substance
If planar memory cell feature size is reduced to increase density, then memory density improves, but fabrication cost and difficulty increase
Solution Approach 1:
Instead of continuously reducing feature sizes in the planar direction, the invention stacks multiple memory layers vertically. This approach increases density by utilizing the third dimension (vertical stacking) rather than pushing the limits of planar lithography, thereby avoiding the increased fabrication difficulty and cost associated with sub-10nm feature sizes.
Solution Approach 2:
The patent forms through-silicon vias (TSVs) and interlayer wiring structures in advance during the stacking process, enabling subsequent layers to be integrated more easily. This preliminary formation of connection paths simplifies the overall fabrication process compared to attempting to create equivalent interconnections after completing all layers.
3Quantity of substance
If 3D stacked memory structure is implemented to increase density, then memory density improves, but wiring complexity through thick layers increases
Solution Approach 1:
The wiring structure is segmented into multiple components: through-silicon vias (TSVs) for vertical connections through thick substrate layers, interlayer wiring structures for connections between stacked layers, and pad structures for external connections. This segmentation of the wiring path into discrete functional elements simplifies the overall wiring complexity by allowing each component to be optimized and manufactured using specialized processes.
Solution Approach 2:
The patent introduces intermediate wiring structures and buffer regions between stacked memory layers. These intermediary elements facilitate signal and power distribution across thick substrate layers by providing localized connection points and reducing the burden on any single through-silicon via, thereby managing wiring complexity in 3D stacked architectures.
Data Source
AI summary
Embodiments of methods and structures for forming a 3D integrated wiring structure are disclosed. The method can include forming a dielectric layer in a first substrate; forming a semiconductor structure having a first conductive contact over a front side of the first substrate; and forming a second conductive contact at a backside of the first substrate, wherein the second conductive contact extends through a backside of the dielectric layer and connects to a second end of the first conductive contact. The 3D integrated wiring structure can include a first substrate; a dielectric layer in the first substrate; a semiconductor structure over the front side of the first substrate, having a first conductive contact; and a second conductive contact at the backside of the first substrate, and the second conductive contact extends through a backside of the dielectric layer and connects to the second end of the first conductive contact.