3D Interconnect Package With Backside Routing for Thermal Reliability
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Solution Overview
Problem
Conventional microelectronic packages are often too large and prone to reliability issues due to thermal expansion, which is a challenge in compacting multiple chips for portable devices and data servers, where a smaller, more reliable, and cost-effective packaging solution is needed.
Innovation Solution
A method involving a microelectronic package with a conductive structure having interconnection elements extending from a base, encapsulated with an encapsulant, and connected to terminals via a redistribution structure, allowing for a compact and reliable assembly with reduced size and manufacturing costs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional chip packages are used with large fan-out areas, then connection to larger arrays on printed circuit boards is achieved, but the package size becomes excessively large and reliability decreases due to thermal expansion effects
Solution Approach 1:
The patent transitions from conventional 2D planar interconnection to 3D vertical interconnection by forming conductive structures that extend through multiple layers and depths within the package. This dimensional change allows fan-out connections to be achieved in the vertical dimension rather than requiring excessive horizontal area, thereby reducing package size while maintaining connection capabilities and improving reliability by minimizing thermal expansion effects.
Solution Approach 2:
The patent implements nested conductive structures where conductive elements are embedded within encapsulant material and arranged in multiple hierarchical levels. The conductive structures are nested within the package volume rather than spreading horizontally, allowing efficient use of three-dimensional space to achieve the required fan-out connections without increasing the package footprint.
2Area of stationary object
If multiple chips are packed into small spaces for portable devices, then device compactness is improved, but manufacturing complexity and thermal management challenges increase
Solution Approach 1:
The patent uses vertical conductive structures extending through multiple layers to interconnect multiple chips in the vertical dimension, allowing dense packing in the horizontal plane without proportionally increasing interconnection complexity. This 3D arrangement enables multiple chips to be interconnected through vertically extending conductive paths rather than requiring complex horizontal routing.
Solution Approach 2:
The patent divides the interconnection system into discrete conductive structures that can be independently formed and positioned. Each conductive structure serves a specific interconnection function, allowing modular assembly and simplifying the manufacturing process despite the high density of connections required for multiple chips in compact spaces.
3Ease of manufacture
If conventional packaging methods are used, then manufacturing processes are well-established, but manufacturing costs and production time increase
Solution Approach 1:
The patent forms conductive structures and positions chips on the carrier in advance before final encapsulation and interconnection steps. This preliminary arrangement of components simplifies subsequent manufacturing steps and enables more efficient production by preparing the package structure beforehand rather than requiring complex assembly operations later in the manufacturing process.
Data Source
AI summary
A microelectronic assembly comprises a microelectronic element, a redistribution structure, a plurality of backside conductive components and an encapsulant. The redistribution structure may be configured to conductively connect bond pads of the microelectronic element with terminals of the microelectronic assembly. The plurality of back side conductive components may be etched monolithic structures and further comprise a back side routing layer and an interconnection element integrally formed with the back side routing layer and extending in a direction away from the back side routing layer. The back side routing layer of at least one of the plurality of back side conductive components overlies the rear surface of the microelectronic element. An encapsulant may be disposed between each interconnection element. The back side routing layer of the at least one of the plurality of back side conductive components extends along one of the opposed interconnection surfaces.