3D Semiconductor Interconnect Bonding to Reduce RC Delay
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Solution Overview
Problem
The semiconductor industry faces challenges in increasing integration density due to high parasitic capacitance and resistance-capacitance (RC) delay in 2D integrated circuit formation, which limits further miniaturization and performance improvement.
Innovation Solution
The method involves forming a semiconductor structure with a first and second tier interconnect structure, where bonding connectors with varying dimensions and orientations are used to reduce line and spacing of interconnecting layers, and through semiconductor vias (TSVs) are employed to enhance electrical connections between tiers, allowing for improved power and signal distribution.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If 2D integrated circuit formation uses smaller spacing between conductive wirings to increase integration density, then more components can be integrated into a given area, but parasitic capacitance between conductive wirings increases and RC delay increases
Solution Approach 1:
The patent transitions from 2D planar interconnect structures to 3D vertically-stacked interconnect structures. Multiple interconnect layers are stacked vertically with through-silicon vias (TSVs) providing vertical inter-layer connections, enabling three-dimensional integration. This dimensional change allows increased integration density without the parasitic capacitance penalties of 2D scaling, as conductors in different vertical layers have reduced parasitic coupling compared to laterally adjacent conductors in the same layer.
2Quantity of substance
If 2D integrated circuit formation uses smaller spacing between conductive wirings to increase integration density, then more components can be integrated into a given area, but leakage current becomes significant
Solution Approach 1:
By stacking interconnect layers vertically in three dimensions, the patent achieves higher integration density without reducing lateral spacing between conductors. The vertical separation between conductors in different layers eliminates the leakage current issues that plague 2D scaling, where conductors are forced into closer lateral proximity.
3Reliability
If through semiconductor vias are employed to enhance electrical connections between tiers, then power and signal distribution is improved, but manufacturing complexity increases
Solution Approach 1:
The patent divides the interconnect structure into discrete modular layers separated by dielectric materials. Each interconnect layer can be independently formed and patterned, and TSVs provide standardized vertical inter-layer connections. This segmentation into manageable layers with repeatable processing steps reduces manufacturing complexity compared to forming complex monolithic 3D structures.
Solution Approach 2:
The patent forms TSVs and lower interconnect layers in advance before stacking upper tiers. This preliminary formation of vertical interconnect structures allows subsequent layers to be aligned and bonded to pre-prepared substrates, simplifying the overall manufacturing process by breaking down complex 3D integration into sequential, manageable stages.
Data Source
AI summary
A manufacturing method of a semiconductor structure includes at least the following steps. Forming a first tier includes forming a conductive via extending from a lower portion of a first interconnect structure into a first semiconductor substrate underlying the lower portion; forming an upper portion of the first interconnect structure on the conductive via and the lower portion; forming a first surface dielectric layer on the upper portion; and forming a first and a second bonding connectors in the first surface dielectric layer. The first bonding connector extends to be in contact with an upper-level interconnecting layer of the first interconnect structure, the second bonding connector is narrower than the first bonding connector and extends to be in contact with a lower-level interconnecting layer of the first interconnect structure, and a top surface of the conductive via is between the upper-level interconnecting layer and the first semiconductor substrate.