3D Interconnect Capacitance Extraction via 2D Slice Segmentation
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Solution Overview
Problem
Current methods for capacitance extraction in integrated circuits, particularly for RF circuits, face challenges in accurately modeling parasitic effects and require extensive computational resources, especially when dealing with large-scale multi-dielectric structures, due to limitations in pattern matching and stochastic solvers.
Innovation Solution
A multi-tier domain pre-characterization method for floating random walk capacitance extraction is introduced, which includes a processor-based system that recursively executes a floating random walk algorithm over a semiconductor structure model, utilizing pre-characterized domains to improve accuracy and convergence time, and rotates domains to align with conductor edges for faster convergence.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If pattern matching methods are used for capacitance extraction, then extraction speed is improved, but accuracy deteriorates for arbitrarily oriented 3D interconnects
Solution Approach 1:
The patent segments the complex 3D interconnect structure into multiple 2D cross-sectional slices at different heights. Each slice is independently processed using pattern matching methods, and the results are integrated to obtain the overall capacitance. This segmentation allows pattern matching to be applied effectively to simpler 2D patterns while maintaining accuracy for the original 3D structure.
Solution Approach 2:
The patent transforms the 3D capacitance extraction problem into a series of 2D problems by taking cross-sectional slices at different heights. This dimensionality reduction allows the use of efficient 2D pattern matching algorithms while capturing the essential 3D effects through integration of multiple slices, thereby improving both speed and accuracy.
2Measurement precision
If discretization-based solvers are used, then measurement precision is improved, but memory requirements and solution time increase prohibitively
Solution Approach 1:
The patent divides the large 3D structure into multiple smaller 2D cross-sectional slices. Each slice requires minimal memory for discretization-based solving, and the results are combined through integration. This segmentation reduces the memory footprint from O(N³) for the full 3D structure to O(n²) for individual 2D slices, making the approach feasible for large-scale circuits.
Solution Approach 2:
By transforming the 3D problem into 2D cross-sectional slices, the patent reduces the computational complexity and memory requirements. The discretization is applied only in two dimensions for each slice rather than three dimensions for the entire structure, significantly reducing memory usage while maintaining accuracy through multi-slice integration.
3Loss of time
If pre-characterized random walk transition domains are used, then convergence time is improved, but pre-computation memory requirements increase
Solution Approach 1:
The patent segments the pre-computation task into 2D cross-sectional slices rather than pre-characterizing the entire 3D structure. This reduces the memory requirements for storing transition domains while maintaining the convergence speed benefits of pre-characterization, as each 2D slice requires significantly less memory than the full 3D domain.
Solution Approach 2:
The patent applies the random walk method in 2D cross-sectional slices rather than in the full 3D space. This dimensionality reduction decreases the number of states that need to be pre-characterized and stored in memory, while still capturing the essential capacitance effects through integration of multiple slices, thereby reducing pre-computation memory requirements.
4Productivity
If domains are rotated to align with conductor edges, then convergence speed is improved, but computational complexity increases
Solution Approach 1:
The patent segments the structure into 2D cross-sectional slices where domain rotation is applied. In each 2D slice, rotating domains to align with conductor edges improves convergence by better capturing the geometric relationships. The segmentation into manageable 2D slices makes the rotation operation computationally feasible compared to rotating in full 3D space.
Data Source
AI summary
An apparatus for extracting capacitances of arbitrarily oriented three-dimensional interconnects includes a processor configured to recursively execute a floating random walk algorithm over a plurality of points for a plurality of conductors, to permit determination of a potential at a plurality of points on a Gaussian surface around each conductor and determination of a coupling capacitance between each conductor. Each iteration includes selecting an initial domain centered about an initial boundary point on a Gaussian surface of an initial conductor, determining a new boundary point on the initial domain from which a successive domain centered about the new boundary point may be selected, and determining a corresponding successive boundary point on the successive domain, each iteration continuing until the new boundary point or the corresponding successive boundary point terminates on a boundary having a known potential. Each selected domain may be rotated to align with the nearest conductor.