3D Interconnect Layout for High-Density Chiplet Power and Signal Routing
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Solution Overview
Problem
Current semiconductor packaging technologies face limitations in increasing input/output density and reducing power delivery issues in compact electronic devices, particularly due to constraints in 2D interconnect configurations that lead to lower IO density, longer routing lengths, and interference between metal routing lines.
Innovation Solution
The implementation of 3D interconnect structures within semiconductor packages, including power bars, power planes, and stacked vias, which allow for vertical routing and improved power and signal delivery, reducing routing length and increasing IO density while avoiding interference with high-performance logic areas.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If 2D interconnect configurations are used, then manufacturing is simpler, but input/output density is lower and routing lengths are longer
Solution Approach 1:
The patent transitions from traditional 2D interconnect routing to 3D interconnect structures, adding a vertical dimension to the routing architecture. This enables signals and power to travel through multiple layers and via holes, dramatically increasing the number of I/O connections per unit area while managing routing complexity through structured layer stacking.
Solution Approach 2:
The interconnect structure embeds multiple functional layers within each other, with signal layers, power layers, and ground layers nested in a hierarchical arrangement. Via holes penetrate through these nested layers to establish vertical connections, effectively packing more interconnect functionality into a compact three-dimensional space.
2Productivity
If more dies are integrated within a single package, then performance and features increase, but power delivery issues worsen
Solution Approach 1:
The power delivery network is segmented into multiple dedicated power layers and ground layers stacked vertically. This segmentation creates multiple independent power delivery paths to different die regions, reducing current density on any single path and improving overall power delivery efficiency to multiple integrated dies.
Solution Approach 2:
Power and ground connections are extended into the vertical dimension through stacked via holes and multi-layer power/ground planes. This three-dimensional power distribution architecture provides shorter and more direct power delivery paths compared to lateral 2D routing, reducing resistive losses and improving power efficiency.
3Length of stationary object
If 3D interconnect structures are implemented, then routing length is reduced, but manufacturing complexity increases
Solution Approach 1:
The patent utilizes vertical via holes to create direct three-dimensional routing paths between layers, dramatically shortening the lateral distance signals must travel. This vertical routing approach reduces overall routing length while the standardized multi-layer fabrication process manages manufacturing complexity through established semiconductor manufacturing techniques.
4Quantity of substance
If metal routing lines are placed closer together to increase density, then input/output density improves, but interference between routing lines increases
Solution Approach 1:
The patent separates conflicting signal routes by placing them on different vertical layers, with via holes providing controlled transitions between layers. This vertical stratification allows high-density routing on each layer while maintaining electrical isolation between adjacent layers through dielectric materials, reducing crosstalk and interference.
Solution Approach 2:
Dielectric materials and ground/power layers act as intermediary shielding between adjacent signal routing lines on different layers. These intermediate layers provide electrical isolation and reference planes that reduce electromagnetic interference between densely packed routing lines, enabling higher density without proportionally increasing interference.
Data Source
AI summary
Electronic package structures and systems are described in which a 3D interconnect structure is integrated into a package redistribution layer and/or chiplet for power and signal delivery to a die. Such structures may significantly improve input output (IO) density and routing quality for signals, while keeping power delivery feasible.