3D IC Interconnects with Compliant Dielectric
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Solution Overview
Problem
Current 3D IC packaging techniques face challenges such as high costs, complex manufacturing processes, and interconnect failures due to thermal and vibrational stresses, making it difficult to achieve cost-effective and reliable integration of multiple chips like image sensors and processors.
Innovation Solution
A method of forming a microelectronic assembly by creating a cavity in a crystalline substrate with interconnects through it, using compliant dielectric and conductive materials to reduce stress and enhance connectivity, allowing for efficient stacking and integration of IC devices like image sensors and processors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If existing 3D IC packaging techniques (Via-First, Via-Last, Via-middle processes) are used to form through-silicon via's, then interconnects can be formed between stacked chips, but the manufacturing process becomes inherently complex and costly
Solution Approach 1:
The patent extracts the lithographic process from the TSV formation process, replacing it with mechanical drilling and electroplating. This removes the complex semiconductor lithography infrastructure requirement while maintaining the ability to form through-silicon via's for interconnects between stacked chips
Solution Approach 2:
The patent replaces the electromagnetic/lithographic system with a mechanical system consisting of drilling, electroplating, and wire bonding. This substitution eliminates the need for expensive CMOS lithography infrastructure while achieving the same interconnect function
2Reliability
If conventional rigid interconnect structures are used in 3D packaging, then interconnects can be formed between chips, but they fail due to thermal and vibrational stresses during manufacturing and operation
Solution Approach 1:
The patent uses wire bonds as flexible interconnect elements that can accommodate thermal expansion and vibrational stresses. The wire bonds provide mechanical compliance that rigid TSV structures cannot achieve, preventing failure under stress conditions
Solution Approach 2:
The patent creates a composite interconnect structure combining rigid TSV's for positioning with flexible wire bonds for electrical connection. This hybrid approach leverages the strengths of both rigid and flexible materials to achieve reliable interconnects under stress
3Volume of moving object
If 3D IC packaging is implemented to stack chips vertically, then space is saved and density increases, but the cost of 3D processing infrastructure becomes prohibitively high
Solution Approach 1:
The patent employs inexpensive, readily available materials and processes (drilling equipment, electroplating baths, wire bonding equipment) instead of expensive lithography infrastructure. These conventional processes are already widely available in manufacturing, eliminating the need for billions of dollars in specialized R&D infrastructure
4Reliability
If through-silicon via's are formed using lithographic processes, then interconnects can be created, but the process is inherently complex and requires billions of dollars in CMOS R&D
Solution Approach 1:
The patent extracts the TSV formation process from the lithography domain and places it in the mechanical/electrochemical domain. This allows companies without billion-dollar CMOS R&D budgets to form through-silicon via's using conventional drilling and electroplating equipment
Solution Approach 2:
The patent replaces the lithographic electromagnetic field system with mechanical drilling and electrochemical plating systems. This substitution makes the technology accessible to companies with conventional manufacturing capabilities rather than requiring specialized semiconductor fabrication infrastructure
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces thermal and mechanical stresses, enhances reliability and yield, provides faster and more reliable signal interconnection, and achieves lower impedance and noise damping, making it suitable for high-speed digital designs.
Implementation Method 1
thermal or vibrational stresses incurred during operation
Implementation Method 2
reduces thermal and mechanical stresses
Implementation Method 3
forming a conductive material along the compliant dielectric material and extending between the first and second surfaces
Implementation Method 4
forming a cavity in a crystalline substrate handler having opposing first and second surfaces, wherein the cavity is formed into the first surface that extends toward but does not reach the second surface
Data Source
AI summary
A microelectronic assembly for packaging/encapsulating IC devices, which includes a crystalline substrate handler having opposing first and second surfaces and a cavity formed into the first surface, a first IC device disposed in the cavity and a second IC device mounted to the second surface, and a plurality of interconnects formed through the crystalline substrate handler. Each of the interconnects includes a hole formed through the crystalline substrate handler from the first surface to the second surface, a compliant dielectric material disposed along the hole's sidewall, and a conductive material disposed along the compliant dielectric material and extending between the first and second surfaces. The compliant dielectric material insulates the conductive material from the sidewall. The second IC device, which can be an image sensor, is electrically coupled to the conductive materials of the plurality of interconnects. The first IC can be a processor for processing the signals from the image sensor.