3D Interconnect Network Layer for Dense Stacking and Lower Thermal Stress
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Solution Overview
Problem
Current 2.5D packaging methods face limitations in vertical interconnect density and thermal stress due to thick RDL interposers, leading to restricted signal bandwidth and performance degradation in 3DIC systems.
Innovation Solution
The use of ion cleaving technology to form a cleave plane in semiconductor substrates, allowing for the creation of an interconnect network layer with high-density, high-bandwidth signal transmission across multiple device elements, spanning both vertical and lateral directions, and incorporating thin, thermally conductive cooling channels.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If thick RDL interposers are used to provide lateral signal connections, then lateral connectivity is improved, but vertical interconnect density decreases and thermal stress increases
Solution Approach 1:
The patent transitions from conventional 2.5D packaging with thick interposers to a 3D stacking architecture where interconnect networks are distributed across multiple thin layers vertically. This dimensional change allows lateral connectivity to be achieved through combined vertical and lateral paths rather than requiring large lateral interposer areas, thereby increasing vertical interconnect density while maintaining lateral connectivity.
Solution Approach 2:
The patent segments the monolithic thick interposer into multiple thin interconnect network layers stacked vertically. Each layer contains a portion of the interconnect network, and the collective effect of all layers provides the required lateral connectivity. This segmentation enables higher vertical interconnect density and reduces thermal stress compared to a single thick interposer.
2Area of stationary object
If thick RDL interposers are used, then lateral signal distribution is improved, but thermal stress and mechanical stress increase
Solution Approach 1:
The patent divides the thick interposer into multiple thin interconnect network layers. This segmentation reduces the thickness of each individual layer, thereby reducing thermal stress and mechanical stress in each layer. The cumulative effect of multiple thin layers maintains the required signal distribution area while reducing overall stress.
Solution Approach 2:
The patent changes the key parameter of interposer thickness from large (30-100 μm) to small (thin layers). This parameter change directly reduces thermal stress and mechanical stress while the stacked architecture maintains the effective signal distribution area through combined lateral and vertical interconnect paths.
3Ease of manufacture
If via depth to thickness ratio is 10:1 in conventional interposers, then manufacturing is simplified, but connection density decreases
Solution Approach 1:
The patent segments the deep via structure into multiple shallow via structures distributed across thin stacked layers. Each layer has a via depth to thickness ratio of 2:1 or greater, which is manufacturable, while the collective arrangement of multiple layers achieves the high connection density that would be impossible with a single thick interposer and deep vias.
Solution Approach 2:
The patent moves the interconnect structure from a single-plane 2.5D architecture to a multi-layer 3D architecture. This allows connection density to be increased by utilizing the vertical dimension for stacking multiple interconnect networks, while each individual layer maintains manufacturable via dimensions with depth to thickness ratios of 2:1 or greater.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach significantly increases interconnect density and signal processing bandwidth while reducing thermal stress and mechanical stress, enabling more efficient 3DIC stacking and improved device performance.
Implementation Method 1
implanting ions into the substrate to form a cleave plane in the substrate
Implementation Method 2
incorporating thin, thermally conductive cooling channels
Data Source
AI summary
A three-dimensional integrated circuit (3DIC) includes an interconnect network layer having a first plurality of electrodes on a lower surface, a second plurality of electrodes on an upper surface, and a plurality of connection structures coupling the first plurality of electrodes to the second plurality of electrodes, a lower device structure with upper electrodes respectively bonded to electrodes of the first plurality of electrodes on the lower surface of the interconnect network layer, and an upper device structure with lower electrodes respectively bonded to electrodes of the second plurality of electrodes on the upper surface of the interconnect network layer. The interconnect network layer can link several diverse dies in lateral and vertical directions.