3D IC Package Vertical Interconnects With Horizontal Distribution Layer

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Solution Overview

Problem

In three-dimensional (3D) integrated circuit (IC) packages, there is a challenge in efficiently routing power and signal connections between dies while minimizing the impact on the densely packed logic areas of the lower die, leading to a tradeoff between area efficiency and the availability of resources for vertical connections.

Innovation Solution

The implementation of a 3D IC package with a first package die that includes vertical interconnects extending between its sides to connect to a package substrate and an upper package die, along with a distribution layer of horizontal interconnects on the metallization layers, which distributes power and signals horizontally to reduce congestion and interference with circuit blocks.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If vertical connections are routed through metallization layers on the lower die, then power and signal distribution is achieved, but metal layer congestion increases and interferes with densely packed logic areas

Engineering Contradiction:
Improvepower and signal distributionVSAvoidmetal layer congestion
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent introduces a distribution layer positioned above the metallization layers, creating a new dimensional plane for horizontal interconnects. This allows power and signal distribution to occur in a separate layer space, avoiding congestion in the existing metallization layers while maintaining effective power delivery to vertical interconnects

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

2Reliability

If more vertical interconnects are added to distribute power and signals to the upper die, then connection reliability improves, but the area available for logic circuits on the lower die decreases

Engineering Contradiction:
Improvevertical connection reliabilityVSAvoidarea available for logic circuits
Core Design Contradiction:
ReliabilityVSArea of moving object

Solution Approach 1:

By routing horizontal interconnects in a distribution layer above the metallization layers, the patent enables more vertical interconnects to be placed on the lower die without increasing metal layer congestion. The additional layer provides extra routing capacity, allowing higher density of vertical connections while preserving logic circuit area

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

3Reliability

If horizontal interconnects are routed through existing metallization layers, then power and signal distribution is achieved, but routing congestion increases and performance deteriorates

Engineering Contradiction:
Improvepower and signal distributionVSAvoidrouting efficiency
Core Design Contradiction:
ReliabilityVSProductivity

Solution Approach 1:

The distribution layer provides a dedicated routing plane for horizontal interconnects, separating them from the metallization layers used for vertical connections. This dimensional separation eliminates routing conflicts, improves signal integrity, and enhances overall routing efficiency while maintaining effective power and signal distribution

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Data Source

PatentUS20240282729A1Package dies including vertical interconnects for signal and power distribution in a three-dimensional (3D) integrated circuit (IC) package
Publication Date: 2024.08.22 QUALCOMM INC
  • US20240282729A1 patent drawing
  • US20240282729A1 patent drawing
  • US20240282729A1 patent drawing

AI summary

A 3D IC package includes a first package die having a first side coupled to a package substrate and a second side coupled to a second package die. The first package die includes vertical interconnects to provide interconnections between the second package die and the package substrate. The vertical interconnects each extend vertically between a first die contact on the first side of the first package die and a second die contact on the second side of the first package die. The second package die couples to the second die contacts of the first package die to form power and/or signal interconnects between the package substrate and the second package die. Horizontal interconnects in a distribution layer on the first side of the first package die distribute power and signals horizontally between the first die contacts and the vertical interconnects.