3D Interconnect Routing in Fan-Out Packages to Reduce Warpage
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Solution Overview
Problem
The semiconductor industry faces challenges in achieving high integration density and miniaturization while maintaining reliable electrical connections and reduced warpage in integrated circuits, particularly with the increasing complexity of packaging technologies like Integrated Fan Out (InFO) and Wafer Level Packaging (WLP).
Innovation Solution
The use of interconnect devices with high routing density, formed using techniques such as damascene and dual damascene processes, which include conductive connectors and redistribution layers to create fine-pitch electrical routing, allowing for closer proximity to semiconductor dies and reduced routing distances, thereby improving bandwidth and connection reliability. Additionally, incorporating integrated passive devices (IPDs) or integrated voltage regulators (IVRs) within the package enhances functionality and power integrity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the minimum feature size is reduced to improve integration density, then more components can be integrated into a given area, but manufacturing precision and reliability of electrical connections become more difficult to maintain
Solution Approach 1:
The patent transitions from planar 2D routing to 3D vertical routing by forming conductive vias through molding compound. This allows electrical connections to extend in the vertical dimension, enabling higher integration density without proportionally reducing feature size precision requirements in the lateral plane.
Solution Approach 2:
The patent introduces a molding compound as an intermediary medium that contains embedded conductive pathways. This molding compound acts as a substrate that can be formed with precise features and then used to create reliable electrical connections, decoupling the precision requirements from the final interconnect structure.
2Adaptability or versatility
If more input/output pads are added to increase functionality, then more electrical connections are available, but package size increases
Solution Approach 1:
The patent utilizes the vertical dimension by forming conductive vias through the molding compound to redistribute and fan-out electrical connections. This 3D approach allows multiple I/O pads to be accessed within a smaller lateral footprint, increasing functionality without proportionally increasing package area.
Solution Approach 2:
The patent segments the electrical connection pathways into multiple conductive vias distributed through the molding compound. This segmentation allows I/O pads to be fan-out to different locations in the vertical and lateral dimensions, enabling higher functionality density within a compact package area.
3Speed
If routing distance is reduced to improve bandwidth, then electrical connections are shorter and faster, but device complexity increases
Solution Approach 1:
The patent merges the semiconductor die with the molding compound containing conductive vias into a single integrated package structure. This consolidation eliminates separate packaging layers and reduces overall routing distance, improving bandwidth while managing complexity through integration rather than addition of components.
Solution Approach 2:
The patent introduces vertical conductive vias through the molding compound, creating 3D routing pathways that shorten electrical connection lengths compared to traditional planar routing. This vertical dimension provides direct pathways from semiconductor contacts to external pads, reducing routing distance and improving signal speed.
Data Source
AI summary
A device includes an interconnect device attached to a redistribution structure, wherein the interconnect device includes conductive routing connected to conductive connectors disposed on a first side of the interconnect device, a molding material at least laterally surrounding the interconnect device, a metallization pattern over the molding material and the first side of the interconnect device, wherein the metallization pattern is electrically connected to the conductive connectors, first external connectors connected to the metallization pattern, and semiconductor devices connected to the first external connectors.