3D Interconnect Packaging for Compact Low-Warpage Microelectronic Arrays
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Solution Overview
Problem
Conventional microelectronic packages are bulky and prone to reliability issues due to thermal expansion, which is exacerbated in larger sizes, posing challenges for compact arrangements in portable devices and data servers, and there is a need for thinner, reliable, and cost-effective packaging solutions.
Innovation Solution
A method involving a conductive structure with interconnection elements overlying a microelectronic element, encapsulated with a dielectric material, and a redistribution layer to form external contacts, along with a thermal interface material to manage thermal stress, resulting in a compact and reliable package.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If conventional chip packages are used with large fan-out areas, then connection to larger arrays on printed circuit boards is achieved, but package size increases and reliability deteriorates due to thermal expansion effects
Solution Approach 1:
The patent transitions from conventional 2D planar packaging to 3D vertical stacking architecture. Multiple microelectronic elements are stacked vertically with interconnection structures extending between layers, enabling compact footprint while maintaining high I/O connectivity. This dimensional change allows achieving large array connections without increasing package area, thereby improving reliability by reducing thermal expansion effects.
Solution Approach 2:
The patent implements nested interconnection structures where conductive vias, traces, and interlayer connectors are embedded within encapsulant material and substrate layers. The interconnection elements are nested between microelectronic elements, with lower-level connections supporting upper-level functions. This nesting enables dense integration without increasing package footprint.
2Productivity
If more microelectronic elements are integrated into compact arrangements, then device functionality increases, but manufacturing complexity and thermal management challenges increase
Solution Approach 1:
The patent divides the microelectronic system into discrete stacked layers, each containing specific functional elements. Individual microelectronic elements can be separately manufactured and tested before assembly. The interconnection structures are segmented into layer-specific traces and vias, enabling modular manufacturing and reducing overall system complexity despite high functionality.
Solution Approach 2:
The patent employs universal interconnection structures that serve multiple functions: electrical connectivity between layers, mechanical support, and thermal conduction. The encapsulant material simultaneously provides insulation, structural support, and stress relief. This multi-functionality reduces the number of separate components needed, simplifying manufacturing while maintaining high device functionality.
3Volume of moving object
If package size is reduced for portable devices, then compactness improves, but thermal management and signal integrity become more challenging
Solution Approach 1:
The patent implements localized thermal management by placing thermal vias and heat dissipation structures specifically at high-heat-generation points within the stacked architecture. Different layers use different thermal conduction paths tailored to their specific thermal loads. This localized approach enables effective thermal management in compact volumes without requiring uniform thermal design throughout the package.
Solution Approach 2:
The patent uses composite encapsulant materials combining dielectric properties with thermal conduction capabilities. The interconnection structures incorporate materials with optimized thermal and electrical properties. These composite materials enable simultaneous achievement of electrical insulation, thermal management, and mechanical support in the compact package structure.
Data Source
AI summary
A method of making a microelectronic package includes bonding a conductive structure to a carrier so that the conductive structure overlies a rear surface of a microelectronic element disposed on the carrier and an exposed top surface of the carrier. The conductive structure may be a monolithic structure having a base and a plurality of interconnections extending continuously away from the base toward the carrier. The microelectronic element may be positioned between at least two adjacent interconnections of the plurality of interconnections. The plurality of interconnections and the microelectronic element may be encapsulated with an encapsulant. The conductive structure may be patterned to form external contacts. At least some of the external contacts may overlie the microelectronic element.