3D Interconnect Parasitics Extraction for Curvilinear IC Layouts
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Solution Overview
Problem
Existing parasitic extraction tools struggle to accurately calculate parasitic effects in IC designs with omni-directional and curvilinear interconnects, as they are restricted to Manhattan routing assumptions and face performance issues with field solvers for larger designs.
Innovation Solution
A layout verification tool divides the IC design into tiles, using a solver to compute parasitic values for interconnect segments within neighboring tiles, employing EM solvers or machine-trained networks to calculate self-capacitance and capacitive coupling, applicable to omni-directional and curvilinear interconnects.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If field solvers are used to calculate parasitic effects, then calculation accuracy is improved, but computational burden and memory consumption increase significantly
Solution Approach 1:
The layout is divided into multiple tiles, and each tile is further divided into interconnect segments. This segmentation allows the complex parasitic calculation problem to be broken down into smaller, more manageable sub-problems that can be solved independently and then combined, reducing the overall computational burden and memory requirements while maintaining accuracy.
Solution Approach 2:
The patent transitions from traditional 2D parasitic extraction to 3D parasitic extraction by considering the vertical stacking of interconnect layers. By extruding 2D tiles into 3D volumes and calculating parasitics in three-dimensional space, the method achieves higher accuracy for modern 3D IC designs while using efficient algorithms to manage the increased computational complexity.
2Measurement precision
If field solvers are used for omni-directional designs, then calculation accuracy is improved, but run-time and memory usage increase
Solution Approach 1:
The layout is divided into multiple tiles, and each tile is further divided into interconnect segments. This segmentation allows the complex parasitic calculation problem to be broken down into smaller, more manageable sub-problems that can be solved independently and then combined, reducing the overall computational burden and memory requirements while maintaining accuracy.
Solution Approach 2:
The patent changes the discretization parameters adaptively based on the local geometry of interconnect segments. By adjusting panel size and density according to the specific characteristics of each segment (such as curvature and proximity to other conductors), the method achieves high accuracy where needed while using coarser discretization elsewhere, thereby reducing overall run-time and memory usage.
3Measurement precision
If smaller panels are used in EM solver input data, then output accuracy is improved, but run-time and memory usage increase
Solution Approach 1:
The patent applies different levels of discretization fineness to different regions of the layout based on local geometric characteristics. In regions with complex geometries, sharp corners, or close spacing between interconnects, finer panels are used to capture the electromagnetic field variations accurately. In regions with simple geometries and larger spacing, coarser panels suffice, thereby maintaining accuracy where needed while improving overall extraction efficiency.
Solution Approach 2:
The patent changes the discretization parameters adaptively based on the local geometry of interconnect segments. By adjusting panel size and density according to the specific characteristics of each segment (such as curvature and proximity to other conductors), the method achieves high accuracy where needed while using coarser discretization elsewhere, thereby reducing overall run-time and memory usage.
4Productivity
If pattern matching techniques are used, then extraction speed is improved, but applicability is limited to certain layout techniques
Solution Approach 1:
The patent creates a universal parasitic extraction method that can handle multiple layout styles including Manhattan routing, omni-directional routing, and curvilinear interconnects. By using 3D geometric modeling and numerical integration techniques rather than pattern matching, the method achieves layout-agnostic parasitic extraction, making it applicable to diverse design styles while maintaining reasonable extraction speed through efficient algorithms.
Data Source
AI summary
Some embodiments provide a method for calculating parasitic parameters for an IC design layout having interconnects that traverse multiple interconnect layers. The interconnects represent wires that traverse multiple wiring layers of the IC. The method divides the layout into 3D tiles such that each of a set of the interconnects is divided into multiple segments each of which is located in a 3D tile. Each 3D tile includes segments of a wiring layer. For a segment located in a particular 3D tile, the method computes parasitic values representing parasitic effects exerted on the segment by other segments in the particular 3D tile and a set of neighboring 3D tiles, including tiles with segments of the same wiring layer and tiles with segments of at least one other wiring layer. The method uses the set of parasitic values to determine parasitic effects exerted on an interconnect to which the segment belongs.