3D Electrochemical Printing of Semiconductor Interconnects Without Lithography
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Solution Overview
Problem
Existing semiconductor interconnect formation processes, such as Damascene and through resist processing, require multiple ancillary steps and equipment, including photoresist lithography, etching, and chemical mechanical polishing, which are costly and time-consuming, and do not efficiently produce high-resolution, low-cost interconnects.
Innovation Solution
A direct electrochemical printing process using an anode substrate with controlled anodes and electrolyte solution to deposit metal interconnects directly onto a substrate, eliminating the need for photoresist lithography and other traditional steps, and utilizing inert anodes to maintain consistent deposition quality.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If traditional Damascene processing or resist processing methods are used, then metal interconnects can be formed with acceptable precision, but the process complexity and equipment requirements increase significantly
Solution Approach 1:
The patent extracts and eliminates the photoresist lithography step from the traditional multi-step interconnect formation process. By using direct electrochemical deposition through a mask layer, the invention removes the need for photoresist application, lithography exposure, development, and stripping steps, significantly simplifying the overall process while maintaining manufacturing precision
Solution Approach 2:
The patent merges the masking function and the metal deposition function into a single electrochemical deposition step. The mask layer serves dual purposes: as a pattern definition layer and as a barrier during electrochemical deposition, combining functions that traditionally required separate lithography and deposition steps
2Manufacturing precision
If traditional multi-step processes including CMP are used, then planarization and surface quality are improved, but production time and cost increase
Solution Approach 1:
The patent extracts and eliminates the chemical mechanical polishing (CMP) step from the traditional process sequence. By controlling the electrochemical deposition parameters and using a sacrificial mask layer that can be selectively removed, the invention achieves the desired surface planarity and interconnect formation without requiring subsequent CMP processing
Solution Approach 2:
The patent performs preliminary planarization by controlling the deposition process itself to create uniform metal layers. The electrochemical deposition parameters are optimized to ensure uniform metal distribution and surface quality from the deposition step itself, eliminating the need for post-deposition CMP
3Manufacturing precision
If photoresist lithography and multiple ancillary processes are used, then interconnect patterns can be defined with high resolution, but the number of process steps and equipment requirements increase
Solution Approach 1:
The patent extracts the lithography equipment requirement by replacing photoresist-based pattern definition with direct electrochemical deposition through a pre-formed mask layer. This eliminates the need for lithography tools, photoresist coaters, and developers, reducing equipment complexity while maintaining pattern definition capability
Solution Approach 2:
The patent uses a mask layer that copies the desired interconnect pattern from a previous fabrication step. The mask layer serves as a physical template that defines the deposition pattern, eliminating the need for optical lithography while achieving the same pattern fidelity
4Reliability
If conventional electroplating with PVD metallization is used, then complete electrical connection and bottom-up filling are achieved, but side wall coverage requirements increase process complexity
Solution Approach 1:
The patent extracts the PVD metallization step and replaces it with direct electrochemical deposition. The electrochemical process inherently provides uniform deposition on vertical and horizontal surfaces through ionic conduction, eliminating the need for separate PVD seed layer deposition and barrier layer formation that are required for side wall coverage in conventional processes
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Enables high-resolution, high-productivity metal interconnect formation with reduced equipment and lower costs, achieving semiconductor-scale resolution without the complexity and inefficiencies of traditional methods.
Implementation Method 1
electrolyte solution comprises includes metal cations
Implementation Method 2
direct electrochemical printing process
Data Source
AI summary
A system for printing metal interconnects on a substrate includes an anode substrate. A plurality of anodes are arranged on one side of the anode substrate with a first predetermined gap between adjacent ones of the plurality of anodes. A first plurality of fluid holes have one end located between the plurality of anodes. A plurality of control devices is configured to selectively supply current to the plurality of anodes, respectively. The anode substrate is arranged within a second predetermined gap of a work piece substrate including a metal seed layer. A ratio of the second predetermined gap to the first predetermined gap is in a range from 0.5:1 and 1.5:1. An array controller is configured to energize selected ones of the plurality of anodes using corresponding ones of the plurality of control devices while electrolyte solution is supplied through the first plurality of fluid holes between the anode substrate and the work piece substrate.