Interconnect Redundancy for 3D IC Timing Analysis

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Solution Overview

Problem

Three-dimensional integrated circuits face challenges in signal communication and timing analysis due to the complexity of routing in stacked chips, where Through-Silicon Via (TSV) and micro bumps are used, leading to inefficiencies in interconnect redundancy and timing violations.

Innovation Solution

A computer-implemented method and apparatus for interconnect redundancy and timing analysis that involves setting a Manhattan distance for dummy micro bumps, creating redundant interconnections, performing static timing analysis, and removing redundant paths that violate timing information, using a redundant interconnection device, static timing analyzer, and interconnection removing device to optimize routing paths and chip layouts.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If redundant interconnections are added to improve reliability, then signal communication reliability is improved, but device complexity increases

Engineering Contradiction:
Improvesignal communication reliabilityVSAvoidrouting path complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent segments the routing paths by creating multiple independent redundant interconnection paths between signal bumps and dummy micro bumps. Each redundant path operates independently, allowing the system to maintain reliability while managing complexity through modular path segmentation rather than a single complex redundant structure

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent performs preliminary timing analysis and identifies timing-violating paths before finalizing the design. By预先 (in advance) removing paths that would cause timing violations, the system establishes reliable redundant paths that are guaranteed to meet timing requirements, avoiding the need for complex runtime decision-making

Inventive Principle:
Principle #10Preliminary action

2Reliability

If multiple redundant paths are created to improve signal communication, then reliability is improved, but manufacturing precision requirements increase

Engineering Contradiction:
Improveinterconnect redundancyVSAvoidrouting path precision
Core Design Contradiction:
ReliabilityVSManufacturing precision

Solution Approach 1:

The patent applies local quality by placing dummy micro bumps at specific locations determined by Manhattan distance criteria. Each dummy micro bump is positioned with specific local quality requirements based on its distance from signal bumps, allowing redundant paths to be created with manageable precision requirements rather than uniform high precision across all connections

Inventive Principle:
Principle #3Local quality

Solution Approach 2:

The patent creates more redundant paths than strictly necessary (excessive action) and then removes only those that violate timing requirements. This approach allows the system to start with generous redundancy that compensates for manufacturing variations, then refine by removing only the problematic paths rather than requiring all paths to meet stringent precision criteria from the start

Inventive Principle:
Principle #16Partial or excessive action

3Measurement precision

If comprehensive timing analysis is performed to remove timing-violating paths, then timing accuracy is improved, but loss of time in the design process increases

Engineering Contradiction:
Improvetiming accuracyVSAvoiddesign process time
Core Design Contradiction:
Measurement precisionVSLoss of time

Solution Approach 1:

The patent performs timing analysis and removes timing-violating paths in advance during the design phase, before fabrication. This preliminary action ensures that the final design contains only timing-compliant redundant paths, eliminating the need for time-consuming iterative adjustments or post-fabrication modifications

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The patent extracts and removes only the specific paths that violate timing requirements, rather than reanalyzing or modifying the entire routing structure. By taking out only the problematic paths identified through systematic timing analysis, the process achieves high timing accuracy efficiently without redundant analysis of compliant paths

Inventive Principle:
Principle #2Taking out (Extraction)

Data Source

PatentUS8689160B2Method and apparatus of an integrated circuit
Publication Date: 2014.04.01 IND TECH RES INST
  • US8689160B2 patent drawing
  • US8689160B2 patent drawing
  • US8689160B2 patent drawing

AI summary

A computer-implemented method for interconnect redundancy of a circuit design comprises the steps of setting Manhattan distance being less than or equal to three pitches; placing a plurality of dummy micro bumps on at least one side of a die including a signal bump formed on the at least one side; determining an interconnecting candidate by selecting from the dummy micro bumps, which is distant from the signal bump by the Manhattan distance; and providing a routing path between the at least one interconnecting candidate and the signal bump.