3D Vertical Interconnect Layout With Self-Aligned Transistor Routing
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Solution Overview
Problem
The challenge in semiconductor manufacturing is to overcome scaling limitations in two-dimensional (2D) circuits by transitioning to three-dimensional (3D) integration, particularly for logic chips where transistor stacking is more complex compared to flash memory applications.
Innovation Solution
The implementation of self-aligned metal routing with 360-degree symmetry for 3D vertical transistors, enabling compact circuit layouts and high-density circuit formation by stacking devices vertically, with techniques applicable to various geometries and allowing for N devices to be connected with 3D wiring, where N is any positive integer.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If 3D vertical transistor stacking is implemented, then transistor density is improved, but device complexity increases
Solution Approach 1:
The patent transitions from 2D planar circuits to 3D vertical stacking by extending transistor channels in the vertical dimension. Multiple channel sections are stacked above each other, with source/drain regions and gates positioned at different vertical levels, enabling higher density while maintaining manufacturability through systematic 3D architecture
Solution Approach 2:
The transistor structure is divided into multiple discrete channel sections (first channel section, second channel section, etc.), each with its own source/drain regions and gates. This segmentation allows independent formation and control of each vertical segment, simplifying the fabrication process despite the overall 3D complexity
2Manufacturing precision
If self-aligned metal routing with 360-degree symmetry is used, then manufacturing precision is improved, but ease of manufacture deteriorates
Solution Approach 1:
The metal routing structure is self-aligned to the vertical transistor channels through 360-degree rotational symmetry. The metal layers automatically position themselves relative to the channel sections without requiring additional alignment steps or masks, achieving high precision while simplifying the manufacturing process
Solution Approach 2:
The patent employs 360-degree rotational symmetry in the metal routing architecture, where the metal layers are arranged symmetrically around the vertical channel axis. This symmetric design eliminates the need for complex asymmetric alignment procedures, improving both precision and manufacturability
3Area of stationary object
If vertical device stacking is implemented, then area utilization is improved, but manufacturing precision requirements increase
Solution Approach 1:
The vertical channel thickness is controlled through preliminary epitaxial growth processes that deposit semiconductor layers with precise thickness control before subsequent fabrication steps. This preliminary formation of the channel structure with accurate dimensional control enables vertical stacking while maintaining manufacturing precision
Solution Approach 2:
The patent replaces mechanical measurement and adjustment methods with epitaxial growth techniques for controlling vertical channel thickness. The epitaxial process provides atomic-level precision in thickness control, eliminating the need for mechanical measurement and manual adjustment, thereby achieving both high area utilization and manufacturing precision
Data Source
AI summary
According to an aspect of the disclosure, a semiconductor device is provided. The semiconductor device includes a stack of insulating layers and interconnect layers that are positioned alternatingly over a substrate. The semiconductor device includes a channel structure extending from the substrate and further through the insulating layers and the interconnect layers. The channel structure includes a first channel section positioned over the substrate and coupled to a first group of the interconnect layers, and a second channel section positioned over the first channel section and coupled to a second group of the interconnect layers. The semiconductor device also includes a plurality of contact structures extending from and coupled to the interconnect layers in a staircase configuration such that each of the plurality of contact structures extends from a respective interconnect layer.