3D Interconnect Structure for Stacked Memory Density
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Solution Overview
Problem
In three-dimensional stacked memory devices, the footprint of conductive interconnects reduces memory density and increases costs per bit due to the need for multiple lithographic steps, limiting the number of layers that can be effectively used.
Innovation Solution
A 3D interconnect structure with a small footprint is designed, featuring landing areas and openings in each level that allow conductors to extend through insulating fill, reducing the number of masks required and eliminating critical alignment steps, thereby minimizing the footprint and manufacturing costs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conductive interconnects are used to couple lower levels to decoding circuitry in three-dimensional stacked memory devices, then connectivity between levels is achieved, but the footprint area of these interconnects significantly reduces the memory area available in upper levels
Solution Approach 1:
The patent transitions from planar interconnect layouts to a three-dimensional stacked configuration where interconnects pass vertically through multiple levels via openings and vias. This dimensional change allows interconnects to occupy vertical space rather than horizontal memory area, enabling upper levels to maintain full memory density while achieving necessary connectivity to lower levels and decoding circuitry.
2Manufacturing precision
If multiple lithographic steps are used to implement interconnections in three-dimensional stacked memory devices, then precise alignment and connectivity are achieved, but the manufacturing cost increases
Solution Approach 1:
The patent combines multiple interconnect formation operations into a single lithographic step by defining all necessary openings and vias for lower level connections in one mask pattern. This merging of operations eliminates the need for separate alignment steps, reducing manufacturing complexity and cost while maintaining precise connectivity through the three-dimensional structure.
3Quantity of substance
If the number of levels in the stack is increased to achieve higher density, then storage capacity increases, but the footprint of interconnects reduces the effective memory density and increases cost per bit
Solution Approach 1:
The patent enables scaling to higher numbers of levels by transitioning interconnects from a planar footprint to a vertical three-dimensional configuration. This allows additional levels to be stacked without proportionally increasing the interconnect footprint, as interconnects utilize the vertical dimension for routing. Consequently, memory density and storage capacity increase while cost per bit decreases, overcoming the limitation of prior planar interconnect approaches.
Data Source
AI summary
A three-dimensional 3D interconnect structure with a small footprint is described, useful for connection from above to levels of circuit structures in a multi-level device. Also, an efficient and low cost method for manufacturing the 3D interconnect structure is provided.