3D Inter-Die Interface Layout for Lower-Area Semiconductor Stacks
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Solution Overview
Problem
Existing three-dimensional semiconductor integrated circuits face challenges in designing vertically stacked semiconductor devices due to complexity in arranging devices and wirings, leading to increased design complexity and area occupation.
Innovation Solution
A three-dimensional semiconductor integrated circuit with a simplified inter-layer interconnection using a template pattern that includes a top die with micro cells and micro bumps connected via a wiring pattern in a tree structure, and a bottom die with macro cells, reducing design complexity and area overhead.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If vertically stacked semiconductor devices are implemented to reduce package area, then area occupation is reduced, but design complexity increases
Solution Approach 1:
The patent segments the semiconductor device into multiple independent dies (first die, second die, third die) stacked vertically. Each die can be designed and manufactured separately, then integrated through TSV connections. This segmentation reduces the overall package area while allowing independent optimization of each die, thereby managing design complexity through modular design.
Solution Approach 2:
The patent transitions from a two-dimensional planar arrangement to a three-dimensional vertical stacking configuration. By utilizing the vertical dimension through TSV (Through-Silicon Via) technology, multiple dies are arranged in the Z-direction rather than expanding in the X-Y plane. This dimensional change achieves area reduction while the standardized inter-die interface templates manage the complexity of vertical integration.
2Speed
If vertically stacked semiconductor devices are implemented to achieve high-speed communication, then communication speed is improved, but design complexity increases
Solution Approach 1:
The device is segmented into functional dies that can be independently optimized for specific functions. The TSV-based interconnect structure segments the signal paths into vertical channels, enabling high-speed communication between stacked dies. Each die can be designed with specialized high-speed interfaces, reducing overall design complexity through functional decomposition.
Solution Approach 2:
The patent employs universal inter-die interface templates that can be applied across different die combinations. These standardized templates provide multi-functional interfaces that support various communication protocols and signal types, enabling high-speed communication while reducing design complexity through reusability and standardization.
3Ease of manufacture
If complex wiring arrangements are used for device integration, then integration is achieved, but design complexity increases
Solution Approach 1:
The patent implements preliminary action by pre-defining standardized inter-die interface templates with predetermined wiring patterns and connection configurations. These templates are designed in advance with optimized routing, allowing subsequent die integration to simply connect to the predefined interfaces rather than designing complex wiring from scratch. This reduces design complexity while maintaining integration capability.
Solution Approach 2:
The patent utilizes parameter changes in the TSV structure, such as varying via diameters, depths, and spacing, to optimize wiring density and signal integrity. By adjusting these parameters in the vertical interconnect structure, complex wiring arrangements are simplified into standardized TSV patterns that are easier to manufacture while achieving full integration capability.
Data Source
AI summary
A three-dimensional semiconductor integrated circuit device including an inter-die interface is provided. The device includes a top die including a plurality of micro cells provided on a top surface of the top die, a plurality of micro bumps provided on a bottom surface of the top die, and wiring patterns connecting the plurality of micro cells to the plurality of micro bumps; and a bottom die including a plurality of macro cells provided on a top surface thereof, wherein the plurality of macro cells are electrically connected to the plurality of micro bumps, respectively, wherein a size of a region in which the plurality of micro cells are provided is smaller than a size of a region in which the plurality of micro bumps are provided.