3D Interposer Via Formation Using Laser Drilling and Compliant Dielectric
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional 3D interposers face challenges in manufacturing due to complex and costly semiconductor lithographic processes for through-silicon vias, and thermal stress issues arise from mechanical and thermal mismatches between the interposer and printed circuit boards, limiting their cost-effectiveness and performance.
Innovation Solution
A 3D interposer with a crystalline substrate handler featuring a cavity, insulation material, compliant dielectric material, and electrical interconnects formed through a method involving plasma etching, laser processing, and metalization, which reduces the need for expensive silicon etching and enhances thermal matching with PCBs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional semiconductor lithographic processes are used to form through-silicon vias, then electrical connections can be established, but manufacturing complexity and cost increase significantly
Solution Approach 1:
The patent segments the via formation process into two distinct stages: first forming vias through the silicon substrate using laser drilling, then forming vias through the dielectric layer separately. This segmentation eliminates the need for complex lithographic processes while maintaining electrical connection reliability, directly addressing the contradiction between connection reliability and manufacturing complexity.
Solution Approach 2:
The patent replaces the mechanical lithographic system with a laser-based drilling system. The laser drilling method uses optical energy to ablate material and form vias, substituting the complex mechanical lithographic equipment with a more straightforward laser processing system, thereby reducing manufacturing complexity while maintaining via formation capability.
2Reliability
If conventional interposer materials are used, then electrical connections can be made, but thermal stress increases due to mismatch between interposer and PCB
Solution Approach 1:
The patent employs a composite structure consisting of a silicon substrate layer and a dielectric layer with different thermal expansion properties. This composite material approach allows the interposer to accommodate thermal expansion mismatches between the interposer assembly and the PCB, reducing thermal stress while maintaining electrical connection reliability through the via structures.
3Manufacturing precision
If expensive silicon etching equipment is used, then precise via formation is achieved, but manufacturing cost increases
Solution Approach 1:
The patent replaces expensive silicon etching equipment with laser drilling equipment. The laser drilling process achieves precise via formation through controlled material ablation using optical energy, eliminating the need for costly semiconductor-grade etching tools while maintaining via precision requirements.
Solution Approach 2:
The patent changes the physical parameter used for via formation from chemical etching to thermal ablation. By using laser energy to directly vaporize and remove material, the process achieves precise via formation through controlled thermal parameters rather than chemical reactions, reducing equipment cost while maintaining precision.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach simplifies and cost-reduces the manufacturing of 3D interposers, improves thermal matching, and enhances electrical and mechanical insulation, leading to improved performance and reliability by using less expensive equipment and accommodating thermal expansion mismatches.
Implementation Method 1
laser processing
Implementation Method 2
plasma etching
Implementation Method 3
metalization
Data Source
AI summary
A 3D interposer (and method of making same) that includes a crystalline substrate handler having opposing first and second surfaces, with a cavity formed into the first surface. A layer of insulation material is formed on the surface of the handler that defines the cavity. The cavity is filled with a compliant dielectric material. A plurality of electrical interconnects is formed through the interposer. Each electrical interconnect includes a first hole formed through the crystalline substrate handler extending from the second surface to the cavity, a second hole formed through the compliant dielectric material so as to extend from and be aligned with the first hole, a layer of insulation material formed along a sidewall of the first hole, and conductive material extending through the first and second holes.


