3D Interposer Layout for Compact Semiconductor Passive Integration
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Solution Overview
Problem
Conventional semiconductor devices face challenges in reducing size while maintaining efficiency due to the exponential increase in I/O pins and thermal management needs, leading to inefficiencies in space utilization and electromagnetic interference.
Innovation Solution
The implementation of a Chip on Wafer on Substrate (CoWoS) architecture with vertically arranged passive and active devices, where magnetic core inductors are placed between the interposer and the substrate, and deep trench capacitors are positioned on the interposer, utilizing through-silicon vias for thermal management and reduced electromagnetic interference.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Length of moving object
If devices are reduced in size to meet consumer demand for smaller devices, then device dimensions decrease, but space utilization efficiency and electromagnetic interference management deteriorate
Solution Approach 1:
The patent transitions from traditional planar (2D) device layout to a three-dimensional (3D) vertical arrangement where passive devices are stacked above active devices. This dimensional change allows multiple components to occupy the same footprint area, significantly improving space utilization efficiency while maintaining compact form factor suitable for consumer devices.
Solution Approach 2:
The patent implements a nested structure where passive devices (capacitors, inductors, resistors) are positioned directly above active devices (transistors, diodes) in a vertical stack. This nesting approach allows passive devices to be embedded within the vertical space above active devices, maximizing space utilization without increasing the device footprint.
2Device complexity
If multiple components are arranged in vertical arrangement to improve space utilization, then space efficiency improves, but thermal management challenges increase
Solution Approach 1:
The patent segments the device into distinct functional layers: an active device layer at the bottom and a passive device layer above it. This segmentation allows independent thermal management strategies for each layer, with heat dissipation paths optimized for each device type, thereby addressing thermal management challenges in the vertical arrangement.
Solution Approach 2:
The patent introduces an interlayer structure between active and passive devices that serves as a thermal management intermediary. This interlayer can function as a heat spreader or thermal interface, facilitating heat transfer from the passive device layer to the substrate or active device layer, thereby managing thermal accumulation in the compact vertical structure.
3Ease of manufacture
If conventional planar arrangement is used to simplify manufacturing, then manufacturing process is simpler, but parasitic losses and electromagnetic interference increase
Solution Approach 1:
The patent employs vertical stacking to separate signal paths and reduce parasitic coupling between devices. By positioning passive devices above active devices in the third dimension, the patent minimizes planar parasitic inductance and capacitance effects that are prevalent in conventional lateral arrangements, thereby reducing overall parasitic losses.
Solution Approach 2:
The patent optimizes the vertical positioning and spacing of individual devices within the stack to minimize electromagnetic interference and parasitic effects. Each device is positioned at a specific height and lateral offset to reduce coupling with neighboring devices, achieving low parasitic losses while maintaining compact vertical arrangement.
Data Source
AI summary
A semiconductor device includes an interposer disposed on a substrate. A first major surface of the interposer faces the substrate. A system on a chip is disposed on a second major surface of the interposer. The second major surface of the interposer opposes the first major surface of the interposer. A plurality of first passive devices is disposed in the first major surface of the interposer. A plurality of second passive devices is disposed on the second major surface of the interposer. The second passive devices are different devices than the first passive devices.