3D Interposer Package Layout for Faster Signal Paths
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Solution Overview
Problem
The semiconductor industry faces challenges in achieving high integration density and efficient packaging of electronic components due to limitations in reducing feature size and packaging area, which affects signal transmission speed and reliability in 3D packaging and 3DIC devices.
Innovation Solution
A method of forming a package structure using a redistribution layer (RDL) with multiple dielectric and metallization layers, through substrate vias, and solder regions, along with a bottom die and additional dies bonded via conductive connectors, to create a multi-tiered package structure that enhances signal and power paths, improving communication speed and reducing vertical transmission paths.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If feature size is continuously reduced to increase integration density, then more components can be integrated into a given area, but signal transmission speed and reliability deteriorate due to limitations in packaging area and vertical transmission paths
Solution Approach 1:
The patent transitions from traditional 2D planar packaging to 3D vertical packaging architecture. Multiple tiers (first tier with interposer, second tier with bottom die, third tier with additional dies) are stacked vertically to achieve higher integration density while maintaining efficient signal transmission paths through the vertical dimension rather than expanding horizontally.
Solution Approach 2:
The package structure is divided into multiple functional tiers: first tier (interposer with RDL structure), second tier (bottom die with encapsulant), and third tier (additional dies). This segmentation allows each tier to be optimized independently for its specific function while collectively achieving high integration density and reliable signal transmission.
2Area of stationary object
If packaging area is reduced to create smaller packages, then package size decreases, but signal transmission reliability deteriorates due to longer vertical transmission paths
Solution Approach 1:
By utilizing the vertical dimension with multiple stacked tiers, the patent achieves compact packaging area while maintaining short signal transmission paths through direct vertical interconnections via conductive connectors and through-substrate vias, rather than requiring long horizontal traces in a planar configuration.
Solution Approach 2:
The interposer structure with redistribution layer and through-substrate vias acts as an intermediary that enables efficient electrical interconnection between multiple dies in the vertical stack. This intermediary provides reliable signal transmission paths while allowing compact packaging arrangement.
3Area of stationary object
If multiple dies are stacked vertically to increase integration density, then packaging area is reduced, but manufacturing complexity increases due to multiple bonding and alignment steps
Solution Approach 1:
The interposer structure with pre-formed redistribution layer and through-substrate vias is prepared in advance (first tier) before die stacking. This preliminary preparation of interconnection structures simplifies subsequent die bonding processes by providing ready-made alignment references and electrical interconnection paths, reducing overall manufacturing complexity despite multiple stacking steps.
Data Source
AI summary
Provided are a package structure and a method of forming the same. The package structure includes a first tier, a second tier, and a third tier. The first tier includes an interposer. The second tier is disposed on the first tier and includes a bottom die. The third tier is disposed on the second tier and includes a plurality of first dies and at least one second die. The at least one second die is disposed between the plurality of first dies. The plurality of first dies are electrically connected to the bottom die by a plurality of first connectors to form a signal path, the plurality of first dies are electrically connected to the interposer by a plurality of second connectors to form a power path, and the plurality of first connectors are closer to the at least one second die than the plurality of second connectors.