3D Interposer SiP Module Vertical Component Integration
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Solution Overview
Problem
Semiconductor SiP modules require excessive encapsulant due to taller components, leading to wasted material and increased physical size, as the top surface must be flat to accommodate the tallest component, resulting in inefficient use of package space.
Innovation Solution
The formation of 3D interposer system-in-package (SiP) modules using interposer units with conductive pillars or copper balls as vertical interconnect structures, allowing taller components to be positioned within openings in the substrate, optimizing space usage and reducing encapsulant waste.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the encapsulant surface is planarized to accommodate the tallest component, then the package provides structural support and environmental protection, but excessive encapsulant is wasted over shorter components and the package size increases
Solution Approach 1:
The patent transitions from a traditional planar package topology to a 3D stacked architecture where components are arranged vertically on multiple levels. This dimensional change allows shorter components to be positioned on upper levels rather than requiring excessive encapsulant to fill the height difference on a single plane, thereby reducing encapsulant waste while maintaining structural integrity and environmental protection.
Solution Approach 2:
The package is segmented into multiple vertical levels or tiers, with each level containing components of appropriate heights. This segmentation allows the encapsulant to be optimized for each level independently, reducing the total volume of encapsulant required compared to a single-planar arrangement where the encapsulant must accommodate the tallest component across the entire surface.
2Ease of manufacture
If the package size is increased to accommodate all components with sufficient spacing, then components are properly supported and connected, but the module footprint increases
Solution Approach 1:
The patent employs vertical stacking to arrange components in the Z-dimension rather than spreading them out in the XY-plane. This allows multiple components to occupy the same footprint area by positioning them at different heights, thereby reducing the module footprint while maintaining adequate spacing and connection capabilities through vertical interconnect structures.
Solution Approach 2:
The 3D interposer structure enables nested arrangement where smaller components or interconnect structures are positioned within the vertical space occupied by taller components. This nested configuration maximizes space utilization within the package footprint, allowing more components to be integrated without increasing the overall module area.
3Reliability
If taller components are used to provide necessary functionality, then electrical performance is improved by reducing signal paths, but more encapsulant is required across the entire device
Solution Approach 1:
The patent implements vertical interconnect structures such as conductive pillars and through-silicon vias that enable short signal paths in the vertical dimension. This allows electrical performance to be improved through reduced signal propagation distance while avoiding the need for excessive encapsulant, as the vertical interconnects provide direct pathways without requiring the encapsulant to bridge large horizontal distances.
Data Source
AI summary
A semiconductor device has a first substrate. A first semiconductor component and second semiconductor component are disposed on the first substrate. In some embodiments, a recess is formed in the first substrate, and the first semiconductor component is disposed on the recess of the first substrate. A second substrate has an opening formed through the second substrate. A third semiconductor component is disposed on the second substrate. The second substrate is disposed over the first substrate and second semiconductor component. The first semiconductor component extends through the opening. An encapsulant is deposited over the first substrate and second substrate.


