3D Interposer SiP Layout for Encapsulant Waste Reduction
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Solution Overview
Problem
Semiconductor SiP modules face inefficiencies due to wasted encapsulant material over shorter components, leading to larger device sizes and reduced utilization of package space, as the encapsulant must cover the tallest components, even if shorter components are present.
Innovation Solution
The use of interposer units and a bottom substrate with conductive pillars or copper balls as vertical interconnect structures allows for the efficient use of unused space by enabling the stacking of taller components without increasing the module's thickness, utilizing openings in the substrate for taller components and interposer units over shorter ones.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Stability of the object's composition
If the encapsulant surface is planarized to cover the tallest component, then the package achieves a flat top surface for structural integrity, but encapsulant material is wasted over shorter components and the device size increases
Solution Approach 1:
The patent introduces a recess feature that creates a vertical dimension variation in the encapsulant surface. By forming a recess that extends below the top surface of shorter components, the encapsulant material is strategically positioned only where needed for structural support, eliminating waste over shorter components while maintaining the flat top surface requirement for structural integrity
Solution Approach 2:
The recess feature creates a localized modification in the encapsulant structure. The encapsulant surface is planarized at the top level for structural integrity, but a recess is formed in specific areas to reduce material usage. This local quality change allows the encapsulant to provide structural support where needed while minimizing material waste in areas with shorter components
2Stability of the object's composition
If the encapsulant surface is planarized to cover the tallest component, then the package achieves a flat top surface, but the device physical size becomes larger than necessary
Solution Approach 1:
By introducing a recess that creates a vertical cavity in the encapsulant, the patent reduces the overall volume of the device. The recess allows the encapsulant to maintain its structural flat top surface while reducing material presence in the vertical dimension over shorter components, thereby decreasing the device's physical size
Solution Approach 2:
The encapsulant structure is segmented into different levels: a flat top surface level and a recess level below it. This segmentation allows the encapsulant to fulfill its structural support function at the top surface while reducing material usage in the recess area, effectively decreasing the overall device volume
3Ease of manufacture
If traditional packaging is used with all components on one substrate, then the manufacturing process is simple, but the package space utilization is reduced and signal paths become longer
Solution Approach 1:
The patent segments the component layout by creating a recess area on the substrate where shorter components are positioned. This segmentation allows taller components to be placed in areas without recesses and shorter components to be placed in recess areas, optimizing vertical space utilization while maintaining a straightforward single-substrate manufacturing approach
Solution Approach 2:
The recess feature creates a local modification in the substrate structure to accommodate shorter components. This local quality change optimizes package space utilization by allowing components of different heights to be efficiently arranged, reducing wasted space while keeping the manufacturing process relatively simple
Data Source
AI summary
A semiconductor device has a first substrate and a second substrate. An opening is formed through the second substrate. A first semiconductor component and second semiconductor component are disposed between the first substrate and second substrate. The second substrate is electrically coupled to the first substrate through the first semiconductor component. A first terminal of the first semiconductor component is electrically coupled to the first substrate. A second terminal of the first semiconductor component is electrically coupled to the second substrate. The second semiconductor component extends into the opening. An encapsulant is deposited over the first substrate and second substrate.