3D Interposer Package for Thermal and EMI Shielding
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional plastic ball grid array (PBGA) packages face issues with poor thermal performance, lack of electromagnetic interference (EMI) protection, large size, and limited die size due to mold constraints, which are unsuitable for mobile applications and package stacking.
Innovation Solution
The implementation of a molded ball grid array or conductor posts partially exposed through the package mold compound, allowing for direct interconnections between packages and the use of an interposer substrate for vertical package interconnection, which reduces package size and enhances thermal and EMI shielding.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If conventional PBGA package structure is used with mold cap clamped to substrate, then package can be manufactured with standard process, but package profile height becomes thick and die-to-package size ratio becomes small
Solution Approach 1:
The patent transitions from a conventional planar PBGA structure to a three-dimensional stacked package architecture. Multiple dies are vertically stacked and interconnected through through-substrate vias, transforming the package from a two-dimensional layout to a three-dimensional structure. This dimensional change enables higher integration density without increasing the package footprint, effectively reducing the die-to-package size ratio while maintaining manufacturability through established semiconductor packaging processes.
2Length of stationary object
If mold thickness is reduced to enable thin packages, then package profile height decreases, but manufacturing precision requirements increase and reliability may deteriorate
Solution Approach 1:
The patent divides the package into multiple discrete functional layers including substrate, mold compound, and individual dies that can be independently manufactured and assembled. This segmentation allows each layer to be optimized separately - the substrate can be manufactured with standard thickness tolerances while the overall package achieves thin profile through precise stacking and interconnection of the segmented components, reducing the need for extreme precision in any single manufacturing step.
3Ease of manufacture
If resin substrate and molding compound are used, then package can be manufactured with standard materials, but thermal performance deteriorates due to poor heat conduction
Solution Approach 1:
The patent employs composite material structures combining organic substrates with inorganic heat dissipation elements. Through-substrate vias are filled with conductive materials such as copper or aluminum, creating thermal pathways that bridge the poor thermal conductivity of the resin substrate and molding compound. This composite approach maintains compatibility with standard semiconductor manufacturing processes while significantly improving heat conduction from the active die regions to the package exterior.
4Device complexity
If conventional PBGA structure is used, then package can be manufactured simply, but EMI protection is lacking due to transparency of materials
Solution Approach 1:
The patent implements nested shielding structures where conductive layers are embedded within the package architecture. Ground planes are integrated into the substrate layers, and conductive via structures provide additional shielding pathways. These nested conductive elements create Faraday cage effects that block electromagnetic interference from reaching sensitive internal components, adding EMI protection without significantly increasing overall package complexity or manufacturing difficulty.
Data Source
AI summary
A method of manufacturing an integrated circuit (IC) package is provided. The method includes stacking an interposer substrate and a device structure, the interposer substrate having a first plurality of contact members formed on a first surface of the interposer substrate and the device structure having a second plurality of contact members that are exposed at a surface of the device structure, and laminating the interposer substrate and the device structure such that the first plurality of contact members are physically and electrically coupled to the second plurality of contact members. The interposer substrate is configured such that a circuit member mounted to a second surface of the interposer substrate is electrically coupled to the second plurality of contact members.