3D IC IP Block Folding with Duplicated Pins and TSVs
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Solution Overview
Problem
Current 3D integrated circuit design methodologies fail to effectively address the placement of I/O pins in folded 3D IP blocks, leading to inefficiencies in wirelength, area usage, and the number of through-silicon-vias (TSVs) required for inter-block connections, which hampers the overall quality of 3D IC designs.
Innovation Solution
The methodology involves folding 2D blocks into 3D blocks with multiple tiers, duplicating pins across these tiers, and connecting them using intra-block through-silicon-vias (TSVs) to minimize wirelength and footprint area, allowing for optimized placement and routing within the 3D IC design.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If I/O pins are placed at the perimeter of stacked IC devices using conventional wiring, then the devices can be connected, but the length and width of the assembly increase
Solution Approach 1:
The patent transitions from 2D perimeter-based I/O pin placement to 3D vertical pin placement through the silicon substrate. By utilizing the third dimension (depth) to place pins and route connections vertically through TSVs, the design reduces the lateral footprint area while maintaining connectivity, directly resolving the contradiction between minimizing area and minimizing wirelength.
Solution Approach 2:
The patent embeds TSVs within the silicon substrate body to create vertical interconnects. The I/O pins are nested within the silicon block rather than being placed on the perimeter surface, allowing connections to pass through the interior of the device stack. This nesting approach reduces the external footprint while providing direct vertical pathways for interconnects.
2Area of stationary object
If through-silicon-vias (TSVs) are used to create vertical connections, then the footprint is reduced, but the number of TSVs required increases
Solution Approach 1:
The patent implements duplicated pins across multiple tiers that can serve multiple functions. A single TSV can connect to multiple duplicated pins at different vertical levels, allowing one TSV to fulfill multiple connection requirements. This multi-functionality reduces the total number of TSVs needed compared to conventional approaches where each connection requires a separate TSV.
Solution Approach 2:
The patent creates copies of I/O pins at different vertical tiers within the 3D stack. These duplicated pins can be connected to shared TSVs, allowing multiple pin instances to utilize the same vertical interconnect resource. This copying strategy enables reduction in TSV count while maintaining the necessary number of functional I/O connections.
3Productivity
If block folding is used to create 3D IP blocks, then inter-block nets are reduced, but the placement of I/O pins in folded blocks is not addressed
Solution Approach 1:
The patent divides the folded 3D IP block into multiple tiers, each with its own set of duplicated pins. This segmentation allows independent optimization of pin placement at each tier while maintaining overall connectivity through vertical TSVs. The tiered segmentation approach systematically addresses the I/O pin placement problem that arises from block folding.
Data Source
AI summary
An intellectual property (IP) block design methodology for three-dimensional (3D) integrated circuits may comprise folding at least one two-dimensional (2D) block that has one or more circuit components into a 3D block that has multiple tiers, wherein the one or more circuit components in the folded 2D block may be distributed among the multiple tiers in the 3D block. Furthermore, one or more pins may be duplicated across the multiple tiers in the 3D block and the one or more duplicated pins may be connected to one another using one or more intra-block through-silicon-vias (TSVs) placed inside the 3D block.