3D Bonding of IPD and Active Dies for Shorter Electrical Paths
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Solution Overview
Problem
Conventional methods for forming integrated circuit packages result in long electrical paths between Independent Passive Devices (IPDs) and computing dies, as well as between memory dies and computing dies, leading to degraded computing performance.
Innovation Solution
IPD dies are bonded directly to a device wafer using chip-on-wafer or wafer-on-wafer bonding techniques, forming a 3D structure with shortened electrical paths, and the resulting package is further assembled with additional components like an interposer, package substrate, and power modules to create a system package.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If IPDs are bonded to package substrate using conventional methods, then IPDs can be integrated into the package, but long electrical paths are created between IPDs and computing dies
Solution Approach 1:
The patent transitions from conventional 2D packaging where IPDs are bonded to the package substrate to a 3D stacked architecture where IPD dies are integrated within the stack between active dies and the substrate. This dimensional change allows IPDs to be positioned much closer to the computing dies, significantly shortening electrical paths while maintaining ease of manufacture through standardized bonding processes.
2Ease of manufacture
If memory dies are bonded to package substrate, then memory can be integrated, but long paths between memory dies and computing dies degrade computing performance
Solution Approach 1:
The patent implements 3D stacking where memory dies are positioned vertically adjacent to computing dies within the package stack, rather than being bonded to the distant package substrate. This vertical integration dramatically reduces the physical distance and electrical path length between memory and computing elements, thereby reducing access time while maintaining manufacturing simplicity.
3Ease of manufacture
If conventional packaging methods are used, then manufacturing is simpler, but computing performance is degraded due to long electrical paths
Solution Approach 1:
The patent segments the package into multiple functional layers including active dies, IPD dies, memory dies, and package substrate, stacked in a vertical configuration. This segmentation allows each component to be optimized and manufactured separately using existing processes, then integrated through standardized bonding techniques, achieving both manufacturing simplicity and improved computing performance through shortened electrical paths.
Data Source
AI summary
A package includes a package substrate, an interposer over and bonded to the package substrate, a first wafer over and bonding to the interposer, and a second wafer over and bonding to the first wafer. The first wafer has independent passive device dies therein. The second wafer has active device dies therein.