3D IPD Wafer-Level Packaging for High-Frequency RF Integration
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Solution Overview
Problem
Existing semiconductor packaging technologies face challenges in integrating 3D RF Integrated Passive Devices (IPDs) due to limitations of planar IPDs, which fail to meet high-frequency integration requirements and often deteriorate performance with additional packaging methods like flip-chip bonding or wire bonding.
Innovation Solution
A wafer-level packaging structure incorporating a molding layer with a 3D IPD structure, featuring first and second metal solder pads, metal pillars, and rewiring layers, allowing for the integration of various electronic components with higher flexibility and compatibility, reducing package size and cost.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If planar IPDs are used on a 2D plane parallel to the silicon substrate, then the packaging structure is simple to manufacture, but the integration requirements of RF packaging structures cannot be met and performance deteriorates at high frequencies
Solution Approach 1:
The patent transitions from planar 2D IPDs to three-dimensional IPD structures. The IPDs are constructed with multiple metal layers (first metal layer, second metal layer, third metal layer) stacked vertically within the molding compound, enabling 3D integration that improves RF performance while maintaining manufacturability through established semiconductor packaging processes.
2Adaptability or versatility
If independent IPDs are fixed to the substrate using flip-chip bonding or wire bonding, then the IPDs can be integrated, but additional packaging space is required and performance deteriorates due to solder balls or wire bonding
Solution Approach 1:
The patent merges the IPD structures directly into the molding compound during the packaging process. The IPDs are formed as integrated structures within the molding layer, eliminating the need for separate mounting steps like flip-chip bonding or wire bonding. This integration approach reduces packaging space by eliminating additional bonding materials and interconnection structures.
3Adaptability or versatility
If independent IPDs are fixed using flip-chip bonding or wire bonding, then the IPDs can be integrated, but solder balls or wire bonding cause deterioration of IPD performance
Solution Approach 1:
The patent combines the IPD structures with the molding compound into a single integrated package. The IPDs are formed within the molding layer using metal layers and dielectric materials, eliminating the need for external bonding connections. This direct integration removes solder balls and wire bonds from the signal path, preserving IPD performance.
4Adaptability or versatility
If 3D IPD structures are integrated into wafer-level packaging, then integration flexibility and compatibility are enhanced, but the manufacturing process becomes more complex
Solution Approach 1:
The patent implements 3D IPD structures by stacking multiple metal layers (first, second, and third metal layers) vertically within the molding compound. This three-dimensional arrangement provides integration flexibility and compatibility with various RF components while using standard semiconductor packaging processes to manage manufacturing complexity.
Data Source
AI summary
A wafer-level packaging structure and a method for preparing the same are provided, the wafer-level packaging structure includes at least a molding layer and a 3D IPD structure fabricated in the molding layer. The wafer-level packaging structure of the present disclosure can integrate various electronic chips and components such as millimeter wave antenna/capacitor/inductor/electric crystal/GPU/PMU/DDR/flash memory/filter, etc., with higher flexibility and wider compatibility, thus reducing package size and package cost.