3D Isolation Structure for Vertically Stacked GAA Transistors
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Solution Overview
Problem
Current semiconductor manufacturing techniques face challenges in scaling transistors beyond single-digit nanometer nodes, as traditional two-dimensional (2D) circuits struggle to increase transistor density, prompting a need for three-dimensional (3D) semiconductor circuits where transistors are stacked vertically.
Innovation Solution
A method involving the formation of an initial stack of layers with substacks separated by transition layers, where vertical channel structures are created and isolated, and sacrificial gate layers are removed to form gate-all-around (GAA) transistors, allowing for the vertical stacking of transistors with isolation structures between them, enabling 3D integration and increased circuit density.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If traditional two-dimensional (2D) circuits are used, then manufacturing processes are simpler, but transistor density cannot be increased beyond single-digit nanometer nodes
Solution Approach 1:
The patent transitions from traditional two-dimensional planar transistors to three-dimensional vertically-stacked transistors. Multiple transistor layers are stacked vertically over a semiconductor substrate, with each layer containing transistors arranged in series or parallel configurations. This vertical stacking enables significantly higher transistor density by utilizing the third dimension (height) rather than only expanding horizontally.
2Quantity of substance
If vertical channel structures are formed, then transistor stacking is enabled, but isolation between neighboring transistors becomes more difficult
Solution Approach 1:
The patent divides the vertically-stacked transistor structure into discrete, isolated units. Each transistor layer is separated from adjacent layers by insulating materials and isolation structures. The channel structures are segmented into individual transistors with distinct source and drain regions, allowing precise electrical isolation between neighboring transistors while maintaining vertical stacking.
Solution Approach 2:
The patent introduces intermediary insulating materials and isolation structures between vertically-stacked transistor layers. These intermediary layers act as electrical barriers that prevent unwanted current flow between adjacent transistors while allowing the vertical stacking architecture to function. The isolation structures include dielectric materials positioned at strategic locations to achieve precise electrical separation.
3Ease of operation
If sacrificial gate layers are removed to form gate-all-around structures, then 360-degree gate control is achieved, but structural support during fabrication is reduced
Solution Approach 1:
The patent employs sacrificial gate layers that are deposited and patterned before the final gate structure is formed. These sacrificial layers provide temporary structural support during the fabrication process, maintaining the integrity of the vertically-stacked transistor architecture. After the surrounding gate structures are formed, the sacrificial layers are removed to create the gate-all-around configuration, having served their supportive function during manufacturing.
Solution Approach 2:
The sacrificial gate layers act as intermediary structures during fabrication. They are temporarily present to provide mechanical support and define the geometry of the vertical channel structures, then are removed to enable the final gate-all-around configuration. This intermediary approach allows the structure to maintain strength during manufacturing while achieving full 360-degree gate control in the final device.
Data Source
AI summary
A method of microfabrication is provided. An initial stack of layers is formed over a semiconductor layer. The initial stack of layers can include a plurality of substacks separated from each other by one or more transition layers. One or more of the substacks include a sacrificial gate layer sandwiched between two first dielectric layers. Openings can be formed in the initial stack of layers so that the semiconductor layer is uncovered. The openings can be filled with vertical channel structures, where each vertical channel structure extends through a respective substack. The initial stack can be divided into separate stacks that include the vertical channel structures surrounded by the substacks and the transition layers. The one or more transition layers can be removed from the separate stacks to uncover transition points between neighboring vertical channel structures. Isolation structures can be formed at the transition points.