3D Integrated Circuits Using Thin Film Transistors for Peripheral Logic
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Solution Overview
Problem
Current 3D memory devices face challenges in reducing die area required for peripheral circuitry, such as control logic, decoder logic, drivers, sense circuitry, and I/O circuits, which increases the cost and complexity of memory devices due to the need for significant space on the die for these components.
Innovation Solution
The use of thin-film transistors (TFTs) to decouple memory arrays and logic circuitry from an insulator substrate, allowing TFTs to be positioned above or below memory cells, thereby reducing the die area needed for peripheral circuitry and increasing memory density.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If conventional transistors are used for control logic and peripheral circuits in 3D memory devices, then functional performance is maintained, but die area increases and manufacturing cost increases
Solution Approach 1:
The patent positions TFT-based peripheral circuits in the vertical dimension above or below the memory array rather than placing them laterally adjacent to the array. This vertical stacking approach eliminates the need for lateral expansion of the die area while maintaining all necessary control logic functions.
Solution Approach 2:
The patent transitions from conventional crystalline silicon transistors to thin-film transistors, changing the material parameter. TFTs require lower processing temperatures and can be fabricated using different manufacturing processes, reducing overall manufacturing cost while enabling vertical integration.
2Adaptability or versatility
If more die area is allocated to peripheral circuitry, then control logic and I/O functions are enhanced, but memory density decreases and cost increases
Solution Approach 1:
By moving peripheral circuits to the vertical dimension through TFT-based stacking, the patent decouples the trade-off between control logic capability and memory density. The memory array maintains its full lateral footprint while TFT circuits occupy the vertical space, enabling both high density and enhanced control functions.
Solution Approach 2:
The patent segments the device into distinct functional layers: the memory array occupies the lateral plane while TFT-based peripheral circuits are separated into vertical layers above or below. This segmentation allows each component to be optimized independently without compromising the other.
3Area of stationary object
If TFTs are positioned above or below memory cells, then die area for peripheral circuitry is reduced, but interconnect complexity increases
Solution Approach 1:
The patent merges the interconnect structures by having TFT circuits share the same bit lines and word lines as the memory array. This consolidation eliminates the need for separate lateral interconnect routes, reducing overall interconnect complexity despite the vertical positioning of TFTs.
Data Source
AI summary
An integrated circuit which enables lower cost and improved features compared to standard crystalline silicon integrated circuits by utilizing thin film transistors (TFTs) in 2D and 3D memory and logic devices, including NAND flash memory and other nonvolatile memories such as RRAM, NRAM, MRAM, FeRAM or PCRAM. By utilizing TFTs, density is improved and die area and costs are reduced. Volumetric memory arrays of several layers may be fabricated with greatly reduced area requirements for periphery circuits and routing. Under 5% area requirements are possible. Ultra-wide I/O may be implemented without die area penalty. Vertical TFTs and logic gates provide better density and high speed approaching or exceeding that of crystalline silicon.