3D Lead Frame Power Module Layout for Higher Power Density
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Current power electronics modules suffer from reduced power density due to separated signal-conducting parts from power semiconductors, which also limit optimal semiconductor distribution and thermal influence, largely dependent on lead frame producibility.
Innovation Solution
A continuous DBC printed circuit board with integrated lead frame and a carrier element made of insulating material for three-dimensional power and control routing, using conductor tracks and wire bonds to connect power semiconductors and terminals, eliminating the need for separate signal routing on the board.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If signal-conducting parts are separated from power semiconductors on the printed circuit board, then lead frame producibility is improved, but power density is reduced
Solution Approach 1:
The patent introduces a multi-layer lead frame structure with conductor tracks arranged in different layers and planes. Signal connections are routed through multiple dimensions using vertical vias and horizontal traces, transforming a two-dimensional PCB routing problem into a three-dimensional lead frame architecture. This enables compact signal routing while maintaining close proximity to power semiconductors, thereby preserving high power density while facilitating lead frame manufacturing.
2Device complexity
If signal-conducting parts are separated from power semiconductors, then manufacturing complexity is reduced, but thermal influence is reduced
Solution Approach 1:
The patent merges the signal routing function and thermal management function into a single integrated lead frame structure. The same conductor tracks that carry signals also serve as thermal pathways, and the lead frame simultaneously provides electrical connections and heat dissipation. This integration ensures that signal-conducting parts remain thermally coupled to power semiconductors while maintaining manufacturing simplicity through standardized lead frame fabrication processes.
3Ease of manufacture
If power semiconductors are positioned according to lead frame producibility, then manufacturing ease is improved, but optimal semiconductor distribution is limited
Solution Approach 1:
The patent segments the lead frame into multiple functional layers with independent conductor track systems. Each layer can be optimized for specific functions (power routing, signal routing, thermal management) and semiconductor positions can be independently determined based on electrical and thermal requirements rather than manufacturing constraints. This layered segmentation provides design flexibility while maintaining manufacturing feasibility through standardized fabrication processes for each layer.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Enables optimal semiconductor distribution and enhanced thermal link, achieving higher power density without compromising electrical connections and thermal performance.
Implementation Method 1
a carrier element consisting of an electrically insulating material, on which conductor tracks are provided
Implementation Method 2
wire bonds are provided which electrically connect the conductor tracks of the carrier element to the power semiconductors and/or the gate- and kelvin-source terminals
Implementation Method 3
a continuous DBC printed circuit board having power semiconductors arranged on connecting regions of an uppermost layer
Data Source
AI summary
A power electronics module, having a continuous DBC PCB having power semiconductors arranged on connecting regions of an uppermost layer of said DBC PCB and a lead frame arranged above the power semiconductors for three-dimensional power and control routing, wherein the lead frame has a drain-source connection, which can be brought into electrical contact with a drain-source contact of the PCB, and a load-source connection which is opposite the drain-source connection via the power semiconductors and which is formed from a plurality of subregions, each of which can be brought into electrical contact with one of the power semiconductors, and at least one gate-source terminal and at least one kelvin-source terminal, and a carrier element including an electrically insulating material on which conductor tracks are provided, wherein the carrier element is routed between the power semiconductors in a region between the load-source connection and the drain-source connection.