3D Leadframe Package Layout for High-Voltage Transistor Isolation
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Solution Overview
Problem
Semiconductor power modules face challenges in achieving high electrical, mechanical, and thermal reliability while minimizing electrical failures and inductances for high-speed switching, especially in high-voltage applications.
Innovation Solution
A 3D semiconductor device package design featuring a leadframe with semiconductor devices mounted on opposed surfaces using L-shaped substrates and conductive layers, enabling wireless surface mounting and direct bonding for improved isolation and thermal conductivity, reducing the need for wires and external mounting clips.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If transistors are mounted side-by-side on the same surface of the leadframe, then the device complexity is reduced, but the creepage distance is insufficient for high-voltage applications
Solution Approach 1:
The patent transitions from two-dimensional side-by-side mounting on the same surface to three-dimensional mounting on opposed surfaces of the leadframe. This vertical stacking approach increases the creepage distance between transistors by utilizing the thickness dimension of the leadframe, thereby preventing electrical breakdown in high-voltage applications while maintaining structural compactness.
2Reliability
If wires are used to connect transistors to leadframe leads, then electrical connections are established, but inductances increase and electrical reliability deteriorates
Solution Approach 1:
The patent removes the wire connections from the electrical interconnection system and replaces them with direct bonding between transistor pads and leadframe leads through the substrate. This extraction of harmful wire elements eliminates the inductance associated with wire loops while maintaining reliable electrical connections.
Solution Approach 2:
The substrate acts as an intermediary element that enables direct bonding between the transistor and leadframe without requiring wires. The substrate's conductive layer serves as the mediation path for electrical connections, allowing current to flow directly from the leadframe through the substrate to the transistor terminals, thereby eliminating inductive effects.
3Ease of manufacture
If conventional mounting methods are used, then manufacturing processes are simple, but thermal conductivity and isolation performance are insufficient
Solution Approach 1:
The patent employs a composite substrate structure combining ceramic or metal base material with conductive layers. This composite construction provides simultaneous thermal conductivity for heat dissipation and electrical isolation between opposing surfaces, achieving high thermal reliability and electrical isolation performance while maintaining manufacturability through established ceramic or metal substrate fabrication processes.
Data Source
AI summary
Described implementations provide wireless, surface mounting of at least two semiconductor devices on opposed surfaces of a leadframe, to provide an isolated, three-dimensional (3D) configuration. The described implementations minimize electrical failures, even for very high voltage applications, while enabling low inductance and high current. Resulting semiconductor device packages have mounting surfaces that provide desired levels of isolation and insulation, while still enabling straightforward mounting techniques, such as soldering, as well as high levels of thermal reliability.