3D LLC Cache Chip Architecture for High-Bandwidth Shared Access
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Solution Overview
Problem
Existing LLC implementations face limitations due to the use of MRAM with small capacity and the need for additional NoC to increase bandwidth, which restricts data access efficiency.
Innovation Solution
A three-dimensionally integrated LLC chip with a DRAM wafer and interface logic unit, connected through bonding columns and interfaces, enabling non-shared and shared access modes for high-bandwidth and large-capacity data caching.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Stability of the object's composition
If MRAM is used for LLC data caching, then data retention is improved, but storage capacity is limited
Solution Approach 1:
The patent combines DRAM and MRAM into a hybrid memory architecture, where DRAM provides high-speed volatile storage and MRAM provides non-volatile backup, merging the advantages of both memory types to achieve large capacity while maintaining data retention
Solution Approach 2:
The patent implements a nested memory structure where MRAM is embedded within or alongside DRAM arrays, allowing DRAM to handle frequent access while MRAM provides persistent storage, effectively nesting different memory technologies to solve the capacity-retention contradiction
2Productivity
If NoC is added between MLC and LLC, then bandwidth is increased, but system complexity increases
Solution Approach 1:
The patent extracts the NoC functionality from the traditional CPU-memory hierarchy and integrates it directly into the LLC chip structure, allowing multiple processing assemblies to access the LLC simultaneously through dedicated interfaces, thereby increasing bandwidth while managing complexity through functional integration
Solution Approach 2:
The patent transitions from a traditional linear memory hierarchy to a multi-dimensional parallel architecture where multiple processing assemblies can access the LLC concurrently through different interfaces, effectively adding dimensional complexity to resolve the bandwidth-complexity trade-off
3Adaptability or versatility
If shared storage access is implemented, then resource utilization is improved, but access speed decreases
Solution Approach 1:
The patent segments the LLC storage space into multiple independent banks or regions, allowing different processing assemblies to access different segments simultaneously, thereby maintaining high access speed while achieving shared resource utilization through spatial parallelism
Data Source
AI summary
An LLC chip and a cache system are provided. The LLC chip includes a storage wafer, an interface logic unit and a packaging substrate. The interface logic unit and the storage wafer are arranged in sequence on the packaging substrate. A plurality of processing assemblies is connected to the interface logic unit so as to perform read and write operations on the storage wafer through the interface logic unit. The storage wafer includes at least one storage space. The plurality of processing assemblies performs read and write operations on a specific storage space or any storage space so as to achieve non-shared independent storage access or shared storage access. Signal transmission bandwidth is thus improved by means of the plurality of distributed interfaces, and data is cached by means of a non-shared mode or shared mode so as to increase data accessing efficiency of the processing assemblies.