3D Logic Array Structure Reducing Periphery Line Complexity
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Solution Overview
Problem
The increasing cost of manufacturing high-density memory devices is a result of the need for different manufacturing steps for memory technologies and supporting peripheral circuits, leading to higher expenses and potential compromises in circuitry.
Innovation Solution
A 3D semiconductor device with a 3D logic array structure is introduced, which includes N sets of gate electrodes, an input electrode, and Y output electrodes, connecting to an array structure and periphery line structure, reducing the number of lines in the periphery and thus lowering manufacturing costs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If different manufacturing steps are used for memory technologies and supporting peripheral circuits, then manufacturing flexibility is improved, but manufacturing cost increases
Solution Approach 1:
The patent combines memory cell fabrication and peripheral circuit fabrication into a unified manufacturing process. The 3D stacked architecture allows both memory arrays and peripheral circuits to be formed using the same sequence of manufacturing steps, eliminating the need for separate process lines and reducing overall manufacturing costs while maintaining production flexibility.
Solution Approach 2:
The manufacturing process is designed to be universal, capable of producing both memory cells and peripheral circuits using identical process steps. This multi-functional approach allows a single manufacturing line to handle diverse circuit types without requiring specialized equipment or process variations, thereby reducing costs while maintaining adaptability.
2Adaptability or versatility
If more lines are used in periphery line structure, then connection capability is improved, but device complexity increases
Solution Approach 1:
The patent transitions from a 2D planar layout to a 3D stacked architecture. By stacking memory cells and peripheral circuits in vertical layers, the design achieves high connection capability without increasing the complexity of peripheral line structures on any single layer. The third dimension provides additional routing pathways and reduces interconnect congestion.
Solution Approach 2:
The device is segmented into multiple functional layers stacked vertically. Memory cells are separated from peripheral circuits into distinct layers, with controlled interfaces between them. This segmentation allows each layer to be optimized independently, reducing the complexity of peripheral line structures while maintaining comprehensive connection capabilities through vertical interconnects.
Data Source
AI summary
A 3D semiconductor device and a 3D logic array structure thereof are provided. The 3D semiconductor device includes an array structure, a periphery line structure and a 3D logic array structure. The array structure has Y contacts located at a side of the array structure. Y is within MN-1 to MN. Y, M and N are natural numbers. M is larger or equal to 2. The 3D logic array structure includes N sets of gate electrodes, an input electrode and Y output electrodes. Each set of the gate electrodes has M gate electrodes. The Y output electrodes connect the Y contacts. The M·N gate electrodes and the input electrode connect the periphery line structure.