3D Logic Array SRAM Cell Segmentation for Half Select Disturb
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional six-transistor (6T) and eight-transistor (8T) SRAM cells suffer from half select disturb issues, which affect data stability and noise margin during read and write operations, especially when unselected column memory cells are activated in the same row as a selected cell, leading to leakage currents and potential data misread or miswrite.
Innovation Solution
A three-dimensional (3D) logic array is implemented, where a write word line is activated only for the selected SRAM memory cell and not for unselected cells in the same row, using separate write and read logic arrays to prevent activation of unselected cells, thereby mitigating half select disturb.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a conventional 6T or 8T SRAM cell is used for memory storage, then the memory device can be manufactured with standard processes, but half select disturb occurs affecting data stability and noise margin
Solution Approach 1:
The patent divides the word line activation into separate write word line and read word line segments. The write word line is activated only for the selected column cell, while the read word line is activated for the selected row, preventing simultaneous activation of unselected cells and eliminating half select disturb
Solution Approach 2:
The patent introduces separate write and read word lines as intermediary control signals between the decode logic and the memory cells. This mediation ensures that only the intended selected cell has both its write and read word lines activated, preventing half select disturb on unselected cells
2Quantity of substance
If the memory device geometry is shrunk to increase density, then more memory cells can be packed, but leakage current increases and noise margin decreases
Solution Approach 1:
By segmenting the word line activation into separate write and read controls, the patent enables precise activation of only the selected cell, minimizing leakage current in unselected cells and maintaining noise margin even as device geometry shrinks
Solution Approach 2:
The patent changes the control parameter from single word line activation to dual independent word line activation (write and read), allowing for better control of leakage current and improved noise margin in scaled devices
3Productivity
If a write operation is performed on a selected column cell, then data can be updated, but unselected column cells in the same row experience half select disturb
Solution Approach 1:
The patent segments the write operation control into a dedicated write word line that is activated only for the selected column, preventing half select disturb on unselected columns while maintaining fast write operation speed
Solution Approach 2:
The patent activates the write word line preliminary and specifically only for the selected column before the write operation commences, ensuring that unselected columns remain inactive and avoid half select disturb
4Speed
If a read operation is performed on a selected row, then data can be accessed, but leakage current can affect the stored data if a write operation occurs simultaneously
Solution Approach 1:
The patent segments the read operation control into a dedicated read word line that is activated only for the selected row, preventing leakage current from affecting other rows even during simultaneous write operations, while maintaining fast read access speed
Data Source
AI summary
A method comprises selecting a memory cell included in a memory cell array in which data is to be stored. The memory cell array is connected with a logic gate array. The memory cells of the memory cell array are individually coupled with a corresponding logic gate of the logic gate array by a separate word line output. The method also comprises communicating a write row output signal to the logic gate array. The write row output signal is communicated from a write address row decoder to the logic gate array. The write address row decoder has a plurality of write row outputs coupled with the logic gate array. The method further comprises communicating a write column output signal to the logic gate array. The write column output signal is communicated from a write address column decoder to the logic gate array.