3D Logic Transistor Planes Using Laser-Annealed Polysilicon
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Current microfabrication techniques face challenges in scaling semiconductor devices beyond single-digit nanometer nodes, particularly in creating high-density 3D logic circuits, as traditional CMOS processes become costly and difficult, and existing methods for 3D integration are not effectively applicable to random logic designs.
Innovation Solution
A method involving laser annealing to convert polycrystalline silicon into epitaxial-like or monocrystalline silicon, allowing for the formation of multiple transistor planes by increasing grain size, which enables the growth of additional epitaxial layers and supports the creation of gate-all-around transistor devices, thereby overcoming the limitations of 2D fabrication and achieving higher transistor density in 3D integrated circuits.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If traditional CMOS processes are used for scaling, then signal propagation speed is improved, but manufacturing complexity and cost increase significantly at single-digit nanometer nodes
Solution Approach 1:
The patent transitions from 2D planar transistors to 3D vertically-stacked transistors. Multiple transistor planes are stacked vertically with intermediate transfer layers, enabling continued scaling without further increasing planar manufacturing complexity. The 3D architecture allows signal propagation benefits while avoiding the exponential cost increase of 2D scaling at single-digit nanometer nodes.
2Quantity of substance
If 3D integration is implemented, then transistor density per unit area is increased, but manufacturing difficulty increases for random logic designs
Solution Approach 1:
The 3D structure is segmented into multiple discrete transistor planes separated by intermediate transfer layers. Each plane can be independently formed and processed, then transferred and stacked. This segmentation enables random logic designs to be implemented in 3D by allowing different logic functions to be distributed across different planes, reducing the overall manufacturing difficulty compared to monolithic 3D integration.
Solution Approach 2:
Transistor planes are formed completely on separate substrates before being transferred and stacked. The intermediate transfer layers are prepared in advance to facilitate the transfer process. This preliminary formation of complete transistor planes simplifies the manufacturing of random logic designs, as each plane can be optimized independently before assembly into the final 3D structure.
3Manufacturing precision
If laser annealing is applied to polycrystalline silicon, then grain size is increased to form epitaxial-like layers, but underlying layers may be overheated
Solution Approach 1:
The laser annealing process is applied locally to the polycrystalline silicon layer with precise spatial control. The laser parameters (wavelength, pulse duration, power density) are optimized to heat only the polysilicon layer to the required temperature for grain growth, while the underlying layers remain below their damage thresholds. This local quality control enables grain size increase without overheating underlying structures.
4Area of stationary object
If more transistor planes are stacked vertically, then maximum use of silicon base area is achieved, but process complexity increases
Solution Approach 1:
Multiple transistor planes are nested vertically like dolls, with each plane containing complete transistor structures. The intermediate transfer layers are nested between the transistor planes, creating a compact vertical stack. This nesting approach maximizes the use of silicon base area by stacking planes without requiring lateral expansion, while the modular nested structure helps manage process complexity through standardized repeating units.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the formation of greater than 20 high-quality 3D nanoplanes of silicon substrates, significantly increasing transistor density and improving the performance and reliability of logic and memory devices by creating defect-free, multi-dimensional planes without overheating underlying layers.
Implementation Method 1
annealing the first layer of polycrystalline silicon using laser heating, the laser heating increasing grain size of the first layer of polycrystalline silicon
Implementation Method 2
annealing the first layer of polycrystalline silicon using laser heating
Data Source
AI summary
A method of forming transistor devices is described that includes forming a first transistor plane on a substrate, the first transistor plane including at least one layer of epitaxial film adaptable for forming channels of field effect transistors, depositing a first insulator layer on the first transistor plane, depositing a first layer of polycrystalline silicon on the first insulator layer, annealing the first layer of polycrystalline silicon using laser heating. The laser heating increases grain size of the first layer of polycrystalline silicon. The method further includes forming a second transistor plane on the first layer of polycrystalline silicon, the second transistor plane being adaptable for forming channels of field effect transistors, depositing a second insulator layer on the second transistor plane, depositing a second layer of polycrystalline silicon on the second insulator layer, and annealing the second layer of polycrystalline silicon using laser heating.