3D Logic-Memory Semiconductor Stack for Higher Device Density
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Solution Overview
Problem
Semiconductor manufacturers face challenges in increasing device density and reducing the dimensions of semiconductor structures within electronic devices due to limited space, which hinders the allocation of sufficient computing and memory resources.
Innovation Solution
The solution involves stacking a three-dimensional logic device and a two-dimensional memory device on different layers of a semiconductor structure, with a dielectric structure providing electrical insulation and conductive structures for connections, allowing for increased device density and reduced dimensions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If device dimensions are reduced to increase density, then device density improves, but manufacturing precision requirements worsen
Solution Approach 1:
The patent transitions from two-dimensional planar device layouts to three-dimensional stacked architectures. Multiple logic devices and memory devices are vertically stacked and interconnected through through-silicon vias (TSVs), enabling increased device density without further reducing lateral dimensions. This dimensional change allows manufacturers to maintain acceptable manufacturing precision while achieving higher overall device density through the added vertical dimension.
2Area of stationary object
If device dimensions are reduced to save space, then space utilization improves, but device reliability worsens
Solution Approach 1:
By stacking devices vertically in three dimensions, the patent achieves high space utilization without compromising lateral device dimensions. The vertical interconnections through TSVs maintain reliable electrical pathways while enabling compact form factors. This approach allows sufficient space for robust device design and reliable interconnections without forcing excessive miniaturization that would degrade reliability.
Solution Approach 2:
The patent introduces intermediary structures including TSVs, bonding layers, and insulating materials that facilitate reliable vertical interconnections between stacked devices. These intermediary elements ensure signal integrity and electrical reliability while enabling compact three-dimensional integration, thus maintaining device reliability in space-constrained applications.
3Productivity
If more devices are integrated to improve performance, then computing resources improve, but device complexity increases
Solution Approach 1:
The patent divides the semiconductor structure into distinct functional segments including logic devices, memory devices, and interconnection structures organized in stacked layers. Each segment can be independently designed, manufactured, and tested before integration. This segmentation manages complexity by breaking down the overall system into modular units while achieving high computing resource density through their vertical integration.
Solution Approach 2:
The three-dimensional stacked architecture organizes multiple computing and memory devices vertically, increasing computing resources without proportionally increasing lateral footprint. The systematic arrangement in vertical layers with standardized interconnections through TSVs provides a manageable complexity framework that enables high device integration while maintaining design and manufacturing feasibility.
Data Source
AI summary
Some implementations described herein provide a semiconductor structure. The semiconductor structure may include a logic device disposed, at a first side of the logic device, on a carrier wafer of the semiconductor structure. The semiconductor structure may include a dielectric structure disposed on a second side of the logic device, the second side being opposite the first side. The semiconductor structure may include a memory device formed on the dielectric structure.