3D Redundant Logic Tile Repair for Main Die Arrays
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Solution Overview
Problem
Existing integrated circuit (IC) designs face challenges in efficiently recovering from defective logic tiles without occupying significant area on the primary die, leading to potential loss of functionality and increased costs due to long signal paths and architectural impacts.
Innovation Solution
Implementing a three-dimensional IC die stack configuration with an active interposer die containing redundant logic tiles, which decouples defective logic tiles from the primary die and couples replacement tiles using signal switches, reducing wiring distances and maintaining functionality.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If redundant logic tiles are placed on the primary die to replace defective logic, then repair capability is provided, but significant die area is occupied that could have housed more compute functionality
Solution Approach 1:
The patent moves redundant logic tiles from the 2D plane of the primary die to a separate 3D stacked die structure. This dimensional transition allows the primary die to maintain full compute density while the replacement logic resides on an additional die layer, eliminating area occupation on the primary die and enabling continued expansion of compute functionality.
Solution Approach 2:
The patent introduces an interposer or interface layer that mediates between the primary die and the redundant logic tiles on the secondary die. This intermediary structure enables communication and signal routing between the defective logic location and the replacement logic without requiring direct integration on the same die, thus preserving primary die area while maintaining repair functionality.
2Reliability
If redundant logic is integrated on the primary die, then repair functionality is achieved, but long signal paths and architectural impacts occur
Solution Approach 1:
By transitioning to 3D stacking, the patent physically positions redundant logic tiles closer to their corresponding primary logic tiles in the vertical dimension. This reduces the horizontal signal path length and minimizes routing complexity, as signals can travel vertically through short interconnects rather than across the entire die surface.
Solution Approach 2:
The patent segments the logic tile system into primary functional tiles on one die and redundant replacement tiles on a separate die. This segmentation allows independent optimization of each die's routing while using standardized interconnect interfaces, reducing overall signal path complexity and enabling modular repair architecture.
Data Source
AI summary
An integrated circuit die stack comprises copies of logic tiles of a tiled array architecture of a main die that are located in an interposer die with signal routing configurations provided such that a faulty tile in the main die can be replaced with the redundant logic tile in the interposer die which has the same functions as the faulty tile in the main die. Still another at least one spare active die having redundant tiles therein, may have at least one redundant logic tile different from or the same as the redundant logic tile of the interposer die. Different redundant logic tiles may be located in the same or different at least one spare active die of the die stack. The redundant logic tile may also be used to enhance performance by increasing the number of active processing elements when not needed for replacement of a faulty tile.