3D Memory Channel Isolation for Stable Access Current
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The challenge of improving the integration and operational reliability of semiconductor devices, particularly in three-dimensional structures, is hindered by limitations in memory cell area and inconsistent cell current flow due to varying numbers of drain select transistors being turned on during access operations.
Innovation Solution
A semiconductor device structure featuring a gate structure with isolated channel layers and sub-memory strings, along with a page buffer mechanism that adjusts precharge voltage levels and evaluation periods to compensate for differences in cell current based on the number of drain select transistors turned on.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If three-dimensional stacked memory cell structure is implemented to improve integration, then degree of integration is improved, but manufacturing complexity and operational reliability become problematic due to inconsistent current flow
Solution Approach 1:
The channel layer is divided into multiple independent segments (first channel layer, second channel layer, third channel layer) separated by isolation structures. This segmentation allows independent control and isolation of current paths, ensuring that variations in the number of turned-on drain select transistors do not affect other channel segments, thereby maintaining operational reliability while preserving the high integration benefits of the 3D stacked structure.
Solution Approach 2:
Different regions of the memory device are given different functional properties through the isolation structures that selectively divide channel layers. The isolation structures create local variations in the channel configuration, allowing certain regions to have enhanced current isolation properties while maintaining overall device integration. This local differentiation addresses the reliability issue without compromising the global integration architecture.
2Reliability
If isolation structures are introduced to improve operational reliability, then current flow consistency is improved, but device complexity increases
Solution Approach 1:
The isolation structures are implemented in the vertical dimension by dividing channel layers at different height levels within the 3D stacked architecture. Rather than adding lateral complexity, the patent uses vertical segmentation to isolate channel layers, allowing multiple isolation points without proportionally increasing overall device complexity. This dimensional approach maintains reliability while leveraging the existing 3D structure.
Solution Approach 2:
The isolation structures are integrated within the existing gate and channel layer stack, nesting the isolation function within the conventional memory cell architecture. The first, second, and third channel layers are nested vertically with isolation structures positioned between them, allowing the isolation functionality to be embedded without adding significant external complexity to the device structure.
Data Source
AI summary
A semiconductor device includes a gate structure including a first select line, a second select line, a first wordline, a second wordline, and a third select line. The semiconductor device also includes a first channel layer passing through the second wordline and the third select line. The semiconductor device further includes a second channel layer passing through the first wordline and the first select line, the second channel layer connected to the first channel layer, and a third channel layer passing through the first wordline and the second select line, the third channel layer connected to the first channel layer. The semiconductor device additionally includes an isolation structure that isolates the second channel layer from the third channel layer.