3D Memory Access Transistor Layout for Shared Word Line Selection
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Solution Overview
Problem
Conventional three-dimensional memory devices require multiple word line contact via structures for each memory block, leading to increased staircase area and inefficiencies in memory block selection.
Innovation Solution
The implementation of access transistors between the memory array region and the staircase region, where one word line contact via structure can be used for all memory blocks, reducing the staircase area by allowing a single contact to function as a 'word line gate' for multiple memory blocks.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If multiple word line contact via structures are used for each memory block, then memory block selection is achieved, but staircase area increases
Solution Approach 1:
The patent merges the functions of multiple word line contact via structures into a single contact structure. This single contact structure serves as a word line gate that controls multiple memory blocks simultaneously, eliminating the need for separate contact vias for each block and thereby reducing the staircase area while maintaining memory block selection capability.
Solution Approach 2:
The single word line contact via structure is designed to perform multiple functions: it serves as a common contact for multiple memory blocks and acts as a word line gate that can select different blocks by applying appropriate voltages. This multi-functional design reduces the overall number of contact structures needed in the staircase region.
2Reliability
If multiple word line contact via structures are used for each memory block, then memory block selection is achieved, but device complexity increases
Solution Approach 1:
The patent combines multiple separate contact via structures into a single integrated contact structure. This merger simplifies the device architecture by reducing the number of discrete components and their interconnections, thereby lowering device complexity while preserving the essential memory block selection functionality through the word line gate mechanism.
3Area of stationary object
If a single word line contact via structure is used for all memory blocks, then staircase area is reduced, but memory block selection efficiency must be improved
Solution Approach 1:
The single word line contact via structure is designed as a multi-functional word line gate that can selectively control multiple memory blocks. By applying different voltage levels to this single structure, the system can efficiently select different blocks for read, write, or erase operations, maintaining high selection efficiency while minimizing the staircase area.
Solution Approach 2:
The word line gate structure employs dynamic voltage control to achieve memory block selection. By dynamically adjusting the voltage applied to the single contact structure, the system can selectively activate or deactivate access to different memory blocks, enabling efficient block selection without requiring multiple static contact structures.
Data Source
AI summary
A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers, memory opening fill structures including a respective vertical semiconductor channel and a respective vertical stack of memory elements extending through the alternating stack in a memory array region, via contact structures contacting the stepped surfaces of the electrically conductive layers at each step in a staircase region, and a vertical stack of access transistors located between the staircase region and the memory array region.