3D Memory Capacitor Layout for Higher Capacitance Without Die Growth
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Solution Overview
Problem
Current 3D NAND memory devices face challenges in increasing memory capacity without expanding the circuit area, as the existing design does not efficiently utilize the space above the memory array for additional components like capacitors, leading to potential increases in die size and reduced memory density.
Innovation Solution
The implementation of a capacitor structure in the spare 3D space adjacent to the 3D memory array, utilizing conductive structures separated by dielectric material, which extends from the bottom to the top level of the memory array, allowing for higher capacitance without occupying additional die area and integrating with the control circuitry beneath the memory array.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If a capacitor is added to the 3D NAND memory device to increase memory capacity, then the memory capacity increases, but the circuit area expands and memory density decreases
Solution Approach 1:
The capacitor structure utilizes the vertical dimension by extending conductive structures from the bottom to the top level of the memory array through the dielectric material, effectively using the third dimension (height) to accommodate the capacitor without expanding the horizontal circuit area. This dimensional transition allows the capacitor to be integrated within the existing 3D memory structure footprint.
Solution Approach 2:
The capacitor is nested within the existing memory array structure by placing conductive structures adjacent to and alongside the memory array tiers. The capacitor utilizes the space within the same vertical envelope as the memory array, effectively nesting the capacitor function within the existing structural boundaries without requiring additional external space.
2Quantity of substance
If the memory array is extended vertically to increase capacity, then memory density increases, but the space for additional components like capacitors is reduced
Solution Approach 1:
The conductive structures serve dual functions: they form part of the memory array architecture (as word lines, bit lines, or select gates) and simultaneously form the capacitor electrodes. The dielectric material between these conductive structures serves both as electrical insulation for the memory cells and as the capacitor dielectric, enabling one structure to fulfill multiple functional roles.
Solution Approach 2:
The capacitor structure is merged with the memory array by using the same conductive structures and dielectric material for both memory storage and capacitance functions. The conductive structures that define the memory array geometry are the same structures that form the capacitor plates, combining what would traditionally be separate components into a unified structure.
3Reliability
If traditional capacitor placement is used in the 3D NAND device, then the capacitor function is achieved, but the die size must increase reducing overall device efficiency
Solution Approach 1:
The capacitor is positioned in the vertical space adjacent to the memory array tiers, utilizing the height dimension rather than horizontal plane. The conductive structures extend vertically through the dielectric material from bottom to top levels, creating a capacitor that occupies vertical volume rather than horizontal area, thus maintaining compact die footprint.
Solution Approach 2:
The capacitor structure is localized to specific regions adjacent to the memory array where vertical space is available, rather than uniformly distributing components across the entire die. The conductive structures are placed in specific locations alongside the memory array tiers to form capacitors where space permits, optimizing local space utilization.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables increased capacitance in a compact form, reducing the need for additional die area and enhancing memory density by utilizing otherwise unused space above the memory array, thereby supporting higher memory capacities within the same die size.
Implementation Method 1
the conductive structures separated by dielectric material can be arranged to form a capacitor coupled between nodes configured to provide different voltages
Data Source
AI summary
Memory devices can be structured in a three-dimensional arrangement using a circuit under array (CUA) architecture. The memory array of such a memory device can include memory cells disposed in vertically arranged tiers. With the memory array extending over a substrate, the CUA region under the memory array can include control circuitry for the memory array. A space adjacent the memory array and disposed above the CUA region can include a dielectric material and conductive structures, with the conductive structures extending vertically in the dielectric material and alongside the memory array. The conductive structures separated by the dielectric material can be used as a capacitor coupled between nodes with the nodes configured to provide different voltages. This capacitor can be coupled to a circuit or a connection node below the level of the memory array.