3D Semiconductor Memory With Air-Gap Insulation
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Current two-dimensional memory semiconductor devices face limitations in integration due to high costs of equipment for forming fine patterns, leading to the development of three-dimensional memory devices to enhance performance and reduce costs, while also requiring improved data retention and reduced parasitic resistance and capacitive coupling.
Innovation Solution
A three-dimensional semiconductor memory device with a multi-layered and multi-column active pattern structure, including word lines with a multi-column structure, string selection gates, and an insulating gapfill layer to define air-gaps between word lines, along with a method of fabricating these devices to increase page depth, reduce parasitic resistance, and improve data retention.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If two-dimensional memory semiconductor devices use fine pattern formation to increase integration, then integration density improves, but equipment cost increases significantly
Solution Approach 1:
The patent transitions from two-dimensional planar memory cells to three-dimensional vertically stacked memory cells. Multiple memory cell layers are stacked along the vertical direction, with bit lines, word lines, and selection lines arranged in different vertical levels. This dimensional change allows significant increase in integration density without requiring proportionally finer lateral patterning, thereby avoiding the need for extremely expensive fine pattern formation equipment.
2Quantity of substance
If three-dimensional memory devices increase page depth, then storage capacity improves, but parasitic resistance increases
Solution Approach 1:
The bit line is divided into multiple bit line segments along the vertical direction, with each segment connected to memory cell layers in different vertical levels. String selection lines and block selection lines are used to selectively connect different bit line segments to active patterns. This segmentation allows the bit line to be effectively shortened for each segment, reducing parasitic resistance while maintaining deep page capacity through vertical stacking.
Solution Approach 2:
String selection lines and block selection lines are introduced as intermediary elements between bit lines and active patterns. These selection lines act as switches to selectively connect bit line segments to specific memory cell layers, enabling deep page access while maintaining low resistance paths by keeping each bit line segment relatively short.
3Quantity of substance
If word lines are closely spaced to increase integration, then device density improves, but capacitive coupling between word lines increases
Solution Approach 1:
An insulating gapfill layer is introduced as an intermediary between adjacent word lines. This gapfill layer creates physical separation and reduces direct capacitive coupling between word lines that are closely spaced in the vertical direction. The gapfill layer allows word lines to be densely packed while maintaining electrical isolation, thus enabling high device density without excessive capacitive interference.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution enables increased integration and page depth, reduced parasitic resistance, and improved data retention in three-dimensional semiconductor memory devices, addressing the limitations of two-dimensional devices and enhancing performance and cost-effectiveness.
Implementation Method 1
an insulating gapfill layer to define air-gaps
Data Source
AI summary
According to example embodiments of inventive concepts, a three-dimensional semiconductor device may include: a memory cell array including memory cells that may be arranged three-dimensionally, the memory cell array including a left side opposite a right side, and a top side opposite a bottom side in a plan view; at least one word line decoder adjacent to at least one of the left and right sides of the memory cell array; a page buffer adjacent to the bottom side of the memory cell array; and a string selection line decoder adjacent to one of the top and bottom sides of the memory cell array.