3D Memory Cell Layout With Air Gaps for Lower Bit-Line Capacitance
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Solution Overview
Problem
The challenge in semiconductor memory devices is to increase memory cell density while reducing parasitic capacitance, which is hindered by structural limitations as memory cell sizes are minimized.
Innovation Solution
A semiconductor device design featuring vertically stacked active layers, bit lines, capacitors, and a word line with air gaps to reduce parasitic capacitance and enhance memory cell density, including a method of fabrication involving alternating insulating and sacrificial layers, forming vertical word and back gates, and connecting bit lines parallel to the substrate.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If memory cell size is reduced to increase net die, then productivity is improved, but parasitic capacitance increases and reliability deteriorates
Solution Approach 1:
The patent transitions from planar memory cell layout to three-dimensional vertical stacking. Multiple memory cells are stacked along the vertical direction (third direction D3) using vias and interlayer insulating layers, enabling increased net die and improved integration density while maintaining acceptable parasitic capacitance levels through spatial separation.
Solution Approach 2:
The memory cell structure is segmented into multiple stacked layers with isolation regions between them. Each memory cell is divided into separate vertical segments that can be independently controlled, allowing for reduced parasitic coupling between adjacent cells while maintaining high density.
2Area of moving object
If memory cell size is reduced, then area is improved, but parasitic capacitance between bit lines increases
Solution Approach 1:
Bit lines are arranged in three-dimensional space with vertical separation through different layers. The first bit line and second bit line are positioned at different vertical levels, connected to different active layers, which reduces parasitic capacitance between them while allowing smaller footprint area for each memory cell.
Solution Approach 2:
Interlayer insulating layers and isolation regions are introduced as intermediary structures between bit lines and active layers. These intermediary layers provide electrical isolation and reduce parasitic capacitance coupling between adjacent bit lines while maintaining compact cell area.
3Productivity
If memory cells are vertically stacked, then productivity is improved, but device complexity increases
Solution Approach 1:
The vertically stacked memory cell structure is segmented into modular units with repeating patterns of active layers, interlayer insulating layers, and isolation regions. This modular segmentation simplifies the fabrication process by allowing systematic replication of cell structures while achieving high vertical integration density.
Solution Approach 2:
The vertical stacking architecture provides multi-functionality: it increases memory cell density, reduces parasitic capacitance through spatial separation, and enables independent control of multiple bit lines. The same structural framework serves multiple performance objectives simultaneously.
Data Source
AI summary
The present invention provides a highly integrated memory cell and a semiconductor device including the same. According to an embodiment of the present invention, the semiconductor device comprises: a plurality of active layers vertically stacked over a substrate; a plurality of bit lines connected to first ends of the active layers, respectively, and extended parallel to the substrate; line-shape air gaps disposed between the bit lines; a plurality of capacitors connected to second ends of the active layers, respectively; and a word line and a back gate facing each other with each of the active layers interposed therebetween, wherein the word line and the back gate are vertically oriented from the substrate.