3D Memory Cell Structure With Air-Gap Isolation for Low Parasitic Capacitance
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Solution Overview
Problem
The challenge of increasing memory cell density in semiconductor devices is hindered by structural limitations that make it difficult to reduce parasitic capacitance and increase capacitance as memory cells are miniaturized.
Innovation Solution
A semiconductor device with a three-dimensional structure is fabricated, featuring a lower structure, semiconductor layers, bit lines, word lines, and device isolation layers with air gaps between them, which reduces parasitic capacitance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If memory cell size is reduced to increase net die, then memory cell density improves, but parasitic capacitance increases and capacitance decreases
Solution Approach 1:
The patent transitions from planar memory cell arrangement to three-dimensional vertical stacking, where memory cells are arranged in multiple layers along the vertical direction. This dimensional change allows increased memory cell density without proportionally increasing parasitic capacitance, as the vertical separation between cells reduces capacitive coupling between adjacent cells in the same plane.
Solution Approach 2:
The patent introduces device isolation layers filled with air gaps as intermediary structures between adjacent bit lines and between memory cells. These air gap isolation layers act as mediators that electrically isolate conductive elements, thereby reducing parasitic capacitance between adjacent bit lines and between memory cell components while maintaining compact three-dimensional integration.
2Quantity of substance
If memory cell size is reduced, then more cells fit in the die area, but capacitance increases and performance deteriorates
Solution Approach 1:
By stacking memory cells vertically in three dimensions rather than arranging them in a single planar layer, the patent achieves high integration density while maintaining adequate electrical performance. The vertical stacking with proper isolation ensures that capacitance values remain within acceptable ranges despite the reduced cell footprint.
Solution Approach 2:
Air gap-filled device isolation layers serve as intermediary structures that provide electrical isolation between adjacent conductive elements in the three-dimensional structure. This isolation prevents excessive parasitic capacitance formation, thereby maintaining memory cell performance and reliability while achieving high integration density.
3Quantity of substance
If three-dimensional structure is implemented, then memory cell density increases, but device complexity increases
Solution Approach 1:
The three-dimensional memory structure is segmented into repeating units consisting of alternating layers of sacrificial materials and semiconductor layers. This segmentation allows systematic fabrication through repeated cycles of depositing and etching, making the complex three-dimensional structure manufacturable through standardized process steps rather than requiring entirely new fabrication techniques.
Solution Approach 2:
Sacrificial layers are deposited in advance during the stack formation process, before the actual memory cell structure is finalized. These preliminary sacrificial structures serve as placeholders that guide subsequent etching processes to create the final three-dimensional architecture with air gaps, simplifying the overall fabrication sequence.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This structure enhances memory cell integration and reduces parasitic capacitance, thereby improving memory cell density and performance.
Implementation Method 1
Since the present invention forms an air gap between word lines and bit lines, it is possible to reduce parasitic capacitance
Data Source
AI summary
A semiconductor device comprises a lower structure; a plurality of semiconductor layers laterally oriented in a direction parallel to a surface of the lower structure; a plurality of bit lines connected an end of the semiconductor layers and extending in a direction perpendicular to the surface of the lower structure; word lines extending laterally in a direction crossing the semiconductor layers over the semiconductor layers; and a device isolation layer extending in the direction parallel to the surface of the lower structure to be disposed between the bit lines and the word lines and including air gaps.