3D Memory Air Gap Layers Reduce Coupling Capacitance
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Solution Overview
Problem
As 3D NAND technology advances towards higher density and capacity, the thickness of memory cells needs to be reduced to improve etching and control costs, but this leads to increased coupling between control gates, resulting in larger RC delay and interference during programming operations.
Innovation Solution
A 3D memory device architecture featuring an alternating stack of conductive and air gap layers with etching stop blocks and a channel structure that includes a blocking layer, storage layer, tunneling layer, and channel layer, which reduces coupling capacitance and RC delay by forming air gap layers between conductive layers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If the thickness of each memory cell is reduced to improve etching and control costs, then manufacturing precision and cost control are improved, but coupling capacitance between control gates increases and RC delay becomes larger
Solution Approach 1:
An air gap layer is introduced as an intermediary between adjacent control gates. This air gap layer has lower dielectric constant than conventional dielectric materials, which reduces the coupling capacitance between control gates. The air gap layer acts as a mediator that maintains the thin memory cell structure while minimizing the harmful electromagnetic coupling effect, thereby resolving the contradiction between thinning for manufacturing precision and preventing coupling interference for reliability.
2Productivity
If the thickness of each memory cell is reduced to increase storage density, then productivity and storage capacity are improved, but RC delay increases and programming efficiency deteriorates
Solution Approach 1:
The air gap layer serves as a mediator between control gates in the thinned memory cell structure. By having lower dielectric constant, it reduces the capacitive coupling that contributes to RC delay. This allows the memory device to maintain high storage density through thinning while minimizing the RC delay penalty, thus resolving the contradiction between productivity (storage density) and loss of time (RC delay).
Data Source
AI summary
A three-dimensional (3D) memory device is provided and includes a substrate, an alternating stack and a channel structure. The alternating stack is disposed on the substrate, and the alternating stack includes a plurality of conductive layers and a plurality of air gap layers alternately stacked. The channel structure is disposed on the substrate and extends vertically through the conductive layers and the air gap layers. The alternating stack further includes a plurality of etching stop blocks between the air gap layers and the channel structure.