3D Non-Volatile Memory Air Gap Structure
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Solution Overview
Problem
Conventional 3-D non-volatile memory devices face challenges with RC delay due to high capacitance between word lines, which increases with the number of stacked memory cells, making it difficult to reduce the total thickness of the memory stack and affecting electrical properties.
Innovation Solution
Incorporating an air gap between word line structures, formed by etching and covering with an insulating layer, reduces capacitance and allows for a thinner interlayer dielectric layer without increasing RC delay, thereby simplifying the manufacturing process and reducing costs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the number of stacked memory cells is increased to increase integration degree, then data capacity and integration degree are improved, but total thickness of memory stack is increased making etching more difficult and RC delay worsens
Solution Approach 1:
The patent introduces air gaps in the vertical dimension between word lines to reduce capacitance without increasing horizontal area. This dimensional approach allows maintaining high integration while reducing the electrical interference that complicates manufacturing and testing.
Solution Approach 2:
The patent changes the dielectric parameter by replacing traditional dielectric material with air gaps between word lines. This parameter change reduces the capacitance between adjacent word lines, thereby reducing RC delay and improving signal integrity without affecting the number of stacked memory cells.
2Length of stationary object
If the thickness of interlayer dielectric layer is reduced to reduce total thickness, then manufacturing complexity is reduced, but capacitance between neighboring word lines increases worsening RC delay
Solution Approach 1:
The patent changes the dielectric parameter by replacing traditional dielectric material with air gaps between word lines. This parameter change reduces the capacitance between adjacent word lines, thereby reducing RC delay and improving signal integrity without affecting the number of stacked memory cells.
Solution Approach 2:
The patent extracts the dielectric material between adjacent word lines and replaces it with air gaps. This removal of material eliminates the source of high capacitance between neighboring word lines, solving the RC delay problem while allowing for reduced interlayer dielectric thickness.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The air gap significantly reduces capacitance between word lines to one-third or less, decreasing RC delay, facilitating easier etching, and enhancing the integration and manufacturing efficiency of the memory device.
Implementation Method 1
RC delay may still remain because the capacitance between the neighboring word lines 15 or 15A (as denoted by the capacitor symbol illustrated in FIG. 1B) is great because the interlayer dielectric layer 12 exists between the neighboring word lines 15 and 15A
Implementation Method 2
an air gap formed between the plurality of word line structures
Data Source
AI summary
A three-dimensional (3-D) non-volatile memory device includes a plurality of word line structures extended in parallel and including a plurality of interlayer dielectric layers and a plurality of word lines that are alternately stacked over a substrate, a plurality of channels protruding from the substrate configured to penetrate the plurality of interlayer dielectric layers and the plurality of word lines, and an air gap formed between the plurality of word line structures.